Research

General Interests

• Low Power Digital Circuits
• Computer/Parallel/Reconfigurable Architectures
• Embedded Systems
• CAD and Modeling for VLSI
• Nanoelectronics

Current Work

Low Power Energy Scalable Architecture Exploration

• Modification of an interconnect simulator (IntSim) for reconfigurable architectures and 3D-IC designs
• High level power/area/delay estimation
• Optimization of bus bit width and spacing

Nanowire Transistor Modeling

• TCAD simulation
• SPICE model adaptation

Nanowire Circuits For Energy Harvesting Sensor Networks

• Comparison of power gating techniques
• Reconfigurable interconnect design
• Low power memory

Past Work

Energy Efficient Interconnect Using Pulse Width Modulation (PWM)

• Optimization of PWM circuitry for peak power reduction
• Exploration of various techniques for modulating signal pulse width on-chip