Featured Projects:


A W-band Current Combined Power Amplifier with 14.8dBm Psat and 9.4% Maximum PAE in 65nm CMOS

Z. Xu, Q. J. Gu, and M.-C. F. Chang, "A W-band Current Combined Power Amplifier with 14.8dBm Psat and 9.4% Maximum PAE in 65nm CMOS," IEEE Radio Frequency Integrated Circuits Symposium (RFIC) 2011

This W-band power amplifier delivers up to 14.8dBm saturated output power with over 14dB power gain and better than 9.4% power added efficiency (PAE), which also achieves better than 11.6dBm output P1dB.  A current power combiner is employed to combine the power from two separate PAs. The entire PA core occupies 0.106 mm2 chip area and dissipates about 200mW.

A 100 GHz Integrated CMOS Passive Imager with >100MV/W responsivity,  NEP

Q. J. Gu, Z. Xu, H.-Y. Jian, A. Tang, M.-C. F. Chang, C.-Y. Huang, and C.-C. Nien, "A 100 GHz Integrated CMOS Passive Imager with >100MV/W responsivity, 23fW/Hz NEP," IET Electronics Letters, vol. 47, issue 9, pp. 544-545, 2011, Featured Paper

This CMOS passive  imager integrates LNA, Dicke switch, detector and baseband Programmable Gain Amplifier (PGA) in a single chip, and achieves the NEP of  /  for without/with Dicke switch, responsivity >100MV/W. It also demonstrates 1.96K noise-equivalent temperature difference (NETD) in 30 ms integration time.

200GHz CMOS Amplifier working close to Device fT

Z. Xu, Q. J. Gu, and M. C. Frank Chang, "A 200GHz CMOS Amplifier working close to Device fT," IET Electronics Letters, vol. 47, issue. 11, pp. 639-641, 2011

200GHz CMOS Prescalers with Extended Dividing Range via Time-Interleaved Dual Injection Locking

An Integrated Frequency Synthesizer for 81-86GHz Satellite Communications in 65nm CMOS

A 200GHz CMOS amplifier with compact fully differential configuration is demonstrated in a 65 nm CMOS technology. Accurate device modeling and creative circuit design indicate the amplifier can support gain at frequencies close to device fT. This amplifier has achieved 8.1dB gain at 200GHz and over 20GHz positive gain bandwidth.

A new dynamic frequency divider topology according to a time-interleaved dual-injection locking scheme is created and the prototype is implemented in 65nm CMOS technology. It has demonstrated ultra-high operation speeds up to 208GHz with ultra-wide locking range up to 37GHz, with 2.5mW power consumption.

This frequency Synthesizer, implemented in 65nm CMOS technology, features coarse phase rotation to endow beam forming capabilities. The phase noise is < -83dBc/Hz at 1MHz offset.The measured reference spur is <-49dBc. Total synthesizer power consumption including LO buffers and phase rotators is 65mW at 1V power supply

Generating Terahertz Signals in 65nm CMOS with Negative-Resistance Resonator Boosting and Selective Harmonic Suppression

Terahertz signals have been successfully generated in 65nm CMOS by: 1) stacking a negative-resistance resonator in parallel to the conventional resonant tank to boost the fundamental oscillation to 0.22 THz; and by 2) selectively suppressing the odd and 2nd harmonics to boost the 4th harmonic in the terahertz regime.

Ultra Wide Locking Range and Low Power V-band Divider

A new injection-locked frequency divider (ILFD) circuit topology, by combining the strengths of LC type ILFD (LC_ILFD) and ring oscillator type ILFD (RO_ILFD), is proposed to achieve high speed, low power, wide locking range and accurate quadrature output phases. A prototype is implemented in TSMC 90 nm CMOS to validate the effective locking range of 7.4 GHz (53.4 to 60.8 GHz) with 0 dBm input signal and 5 mW DC power dissipation.

Two 10Gb/s/pin Low-Power Interconnect Methods for 3D ICs

 

  

 

 

Q. Gu, Z. Xu, D. Huang, T. LaRocca, N. Wang, and M.-C. F. Chang, "A Low Power V-Band CMOS Frequency Divider with Wide Locking Range and Accurate Quadrature Output Phases," IEEE Journal of Solid-State Circuits, pp. 991-998, Apr. 2008
Q. J. Gu, H.-Y. Jian, Z. Xu, Y.-C. Wu, F. Chang, Y. Baeyens, and Y.-K. Chen, "CMOS Prescaler(s) with Maximum 208GHz Dividing Speed and 37GHz Time-Interleaved Dual-Injection Locking Range," IEEE TCAS-II, vol.58, no.7, pp. 393-397, July 2011
Z. Xu, Q. J. Gu, Y.-C. Wu, H.-Y. Jian, F. Wang, and M. C. Frank Chang, "An Integrated Frequency Synthesizer for 81-86GHz Satellite Communications in 65nm CMOS," IEEE RFIC Symposium, pp. 57-60, May 2010
Q. J. Gu, Z. Xu, H.-Y. Jian, X. Xu, F. Chang, W. Liu, and H. Fetterman, "Generating Terahertz Signals in 65nm CMOS with Negative-Resistance Resonator Boosting and Selective Harmonic Suppression," IEEE Symposium on VLSI Circuit, pp. 109-110, June 2010

Two capacitive coupling methods are used in creating low-power and high-bandwidth vertical (inter-tier) interconnects in 3DIC: UWB impulse-shaping interconnect (UII) and RF interconnect (RFI). Both interconnects are implemented in MIT-Lincoln Lab 0.18um CMOS 3DIC to realize 10Gb/s/pin and 11Gb/s/pin transmission bandwidths, respectively, with 2.7mW/pin and 4.35mW/pin power consumption.

Q. Gu, Z. Xu, J. Ko, and M.F. Chang, "Two 10 Gb/s/pin Low Power Interconnect Methods for Three-Dimensional Integrated Circuits," IEEE International Solid-State Circuits Conference (ISSCC) Digest of  Technical papers, pp. 448-449, Feb. 2007

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High Speed Integrated Circuits & Systems

High speed integrated circuits & systems

Department of Electrical and Computer Engineering, University of California, Davis, CA 95616