# .synopsys_dc.setup 
# 
# 2010/02/24  search_path set according to 32/64-bit arch, by Zhibin Xiao
# 2009/02/12  Many parts re-written in new tcl version, by Zhibin Xiao
# 2005/02/10  Updated search_path
# 2003/05/14  Changed search_path so it now points to /afs
# 2003/05/14  Written
# 
# "This is an example .synopsys_dc.setup file which should be
# used when transferring designs to Cadence through EDIF."
# 
# 
# 
# Library and Search Path variables */
# 
# search_path = {. /software/synopsys/2000.05/libraries/syn \
#    /home/ee5546/project } 
# search_path = {. /software/synopsys/2000.05/libraries/syn }
# 
# Note: if 32-bit RHEL System, SYSNAME = i386_linux24
#       else 64-bit RHEL 3.0, SYSNAME = ia64_linux26 
#       Please use command: "echo $SYSNAME" to find out.
#       There are two designware libraries for 32-bit and 64-bit machines
#       We need to choose based on the os version defined by variable SYSNAME.

if { [getenv {SYSNAME}] != "ia64_linux26" } {
set search_path [list . /net/pizza/tools/classes/281/lib \
                      /afs/ece/common/pkg/synopsys.2003/libraries/syn \
                      /afs/ece/common/pkg/synopsys.2003/dw/sim_ver ] 
} else {

set search_path [list . /net/pizza/tools/classes/281/lib \
               /.net/pizza/tools/synopsys/syn/B-2008.06/libraries/syn \
               /.net/pizza/tools/synopsys/syn/B-2008.06/dw/sim_ver ] 
}

set link_library [list vtvtlib25.db dw_foundation.sldb]                
set target_library [list vtvtlib25.db]
# set symbol_library = {}

# verilog 

set verilogout_no_tri true

# Read Symbol 

set edifin_lib_route_grid 1024
set vhdlout_use_packages [list IEEE.std_logic_1164, IEEE.std_logic_arith, IEEE.std_logic_textio, vtvtlib25.components]

# Bus Naming variables 
#  Some gave warnings
#set bus_naming_style   "%s<%d>"   # causes Warning
#set bus_naming_style   "%s[%d]"   # causes Error even though default in "sold"
set bus_dimension_separator_style "><"
set gen_bus_member_naming_style "%s<%d>"
set gen_bus_range_naming_style "%s<%d:%d>" 
set bus_extraction_style  "%s<%d:%d>"
# set edifout_array_range_naming_style  "%s<%d:%d>"


# /* Power and Ground variables */
# /*

set edifin_ground_net_name  "gnd!"
set edifin_ground_net_property_name  ""
set edifin_ground_net_property_value  ""
set edifout_ground_name  "gnd"
set edifout_ground_net_name  "gnd!"
set edifout_ground_net_property_name  ""
set edifout_ground_net_property_value  ""
set edifout_ground_pin_name  "gnd!"
set edifin_power_net_name  "vdd!"
set edifin_power_net_property_name  ""
set edifin_power_net_property_value  ""
set edifout_power_name  "vdd"
set edifout_power_net_name  "vdd!"
set edifout_power_net_property_name  ""
set edifout_power_net_property_value  ""
set edifout_power_pin_name  "vdd!"
set edifout_power_and_ground_representation  "net"

# */
# /* Net to Port Connection variables */
# /*

set edifin_autoconnect_ports  "true"
set compile_fix_multiple_port_nets  "true"
set gen_match_ripper_wire_widths  "true"
set link_force_case  "case_insensitive"
set single_group_per_sheet  "true"
set use_port_name_for_oscs  "false"
set write_name_nets_same_as_ports  "true"

# Output variables */

set edifout_netlist_only  "false"
set edifout_target_system  "cadence"
set edifout_instantiate_ports  "true"