Contains all commands needed for simulation and synthesis. You must enter the top-level design name at the top of the file.
Type "make <return>" to see make targets and instructions.
Template used to generate a customized command file for Design Compiler. Do not edit this file unless you are told you need to.
Don't miss this one! Make sure the file begins with a period.
Copy it to your home dir (but then you can't customize it for individual
runs, which is probably ok), or your working dir (make sure you copy it
when you start a new dir).
If you have a .synopsys_dc.setup file in your home directory
(from ECE 180B for example), you will likely need to move it or change
its name so that DC won't get confused.
Do not edit this file unless you are told you need to. Remember that it appears in linux only with "ls -a" and not just "ls".
Very simple example design with 2-bit and 32-bit adders, and registers
Very simple example submodule of abc.v with 2 FFs.
File that contains all source verilog files for simulation (NCVerilog or Verilog-XL).
File that contains all source verilog files for synthesis (Design Compiler). Note: do not include test files.
Very simple test bench file for abc.v and def.v that compiles cleanly.
It contains "62 different functions ranging from buffers to scan flip-flops with set and reset, including specialized low power cells with multiple drive
strength variants, the library includes over 170 different standard cells."
Timing parameters are in units of nanoseconds.
Vdd = 0.95 V, Tj = –125°C),
Vdd = 1.25 V, Tj = –0°C),
Vdd = 0.95 V, Tj = –40.0°C),
Vdd = 1.25 V, Tj = –40.0°C).
Basic configuration changes
command: set clk_period CLKPERIOD" (CLKPERIOD in units of nanoseconds)
Leave at default value unless told to change it.
The Standard Cell Library We Use
Details of the standard cells for Typical speed NMOS, Typical speed PMOS, Vdd = 1.1 V, and Tj = 25.0°C.
Details of the standard cells for five corners:
It contains "62 different functions ranging from buffers to scan flip-flops with set and reset, including specialized low power cells with multiple drive strength variants, the library includes over 170 different standard cells."
Timing parameters are in units of nanoseconds.See the following files for more information on the library's cells. Copies are posted on canvas under "Files"
slow (slow, slow, Vdd = 0.95 V, Tj = –125°C),
fast (fast, fast, Vdd = 1.25 V, Tj = –0°C),
worst_low (worst.low, worst.low, Vdd = 0.95 V, Tj = –40.0°C), and
low_temp (low.temp, low.temp, Vdd = 1.25 V, Tj = –40.0°C).
The file that specifies the logic and the rise and fall times (by the specify block) of the standard cells.
Previously, we used the 0.25 um vtvt library.
(1) lc_shell (2) read_lib NangateOpenCellLibrary_typical_ccs.lib (3) write_lib NangateOpenCellLibrary -output NangateOpenCellLibrary.db OR: write_lib NangateOpenCellLibrary -format dbOther approaches using "read_lib" and "write_lib" did not work for us.
To simulate with gates, add something similar to the test_prac_gates target to your Makefile shown below. The test_prac target is an example of how the test would normally be run with the source verilog files.
test_prac_gates: ncverilog [flags_normally_used] /net/pizza/tools/classes/281/lib/vtvtlib25.v prac.vg prac.vt test_prac: ncverilog [flags_normally_used] prac.v prac.vtwhere prac.vg is your gate netlist and prac.vt is a testbench file. Note that you will likely not be able to view signals inside the gate netlist file without changing your testbench since the names of internal signals will likely change after synthesis.
sold &and selecting the appropriate product.
Two other tools by Synopsys can be used to graphically interact with DC and view netlists.
design_vision design_analyzer===== 2011/02/14
You can also compile your design within design_vision by loading file using the analyze menu and then using the same dc_compile script. It will complain about the /* */ comments in the script file when run this way. It also complains about a "your_library.db" but both can apparently be ignored.
Design Analyzer seems to be not working correctly.
2017/02/04 Major changes for new NanGate 45 nm library 2015/02/03 Added SEQGEN note 2015/01/16 Minor changes 2010/02/17 A few small changes 2010/02/16 Updated path to vtvtlib25.v 2009/02/13 Some updates