synopsys2004After adding the line, log out and log back in for the changes to take effect.
To compile a module 'abc', follow the procedure listed below. Note that the first four steps are prepatory and only step five is needed to perform the compilation. These instructions are printed by typing 'make' by itself.
Basic synthesis procedure for top-level module 'abc': 1) add all submodules to file abc.vf 2) 'make NAME=abc check' 3) 'make NAME=abc new_compile' 4) add appropriate 'analyze' commands to dc-abc.tcl (normally works best if you add one line per *.v file) 5) 'make NAME=abc compile' You can also change 'foo' to 'abc' in 'Makefile' to avoid typing 'NAME' variable each time 1) change 'NAME := foo' to 'NAME := abc' in Makefile 2) add all submodules to file abc.vf 3) 'make check' 4) 'make new_compile' 5) add appropriate 'analyze' commands to dc-abc.tcl (normally works best if you add one line per *.v file) 6) 'make compile'
sold &and selecting the appropriate product.
Two other tools by Synopsys can be used to graphically interact with DC and view netlists.
design_vision design_analyzer===== 2011/02/14
You can also compile your design within design_vision by loading file using the analyze menu and then using the same dc_compile script. It will complain about the /* */ comments in the script file when run this way. It also complains about a "your_library.db" but both can apparently be ignored.
Design Analyzer seems to be not working correctly.
To simulate with gates, add something similar to the test_prac_gates target to your Makefile shown below. The test_prac target is an example of how the test would normally be run with the source verilog files.
test_prac_gates: ncverilog [flags_normally_used] /net/pizza/tools/classes/281/lib/vtvtlib25.v prac.vg prac.vt test_prac: ncverilog [flags_normally_used] prac.v prac.vtwhere prac.vg is your gate netlist and prac.vt is a testbench file. Note that you will likely not be able to view signals inside the gate netlist file without changing your testbench since the names of internal signals will likely change after synthesis.
J. B. Sulistyo and D. S. Ha, "Developing Standard Cells for TSMC 0.25um Technology under MOSIS DEEP Rules", Department of Electrical and Computer Engineering, Virginia Tech, Technical Report VISC-2002-01, January 2002.
2010/02/17 A few small changes. 2010/02/16 Updated path to vtvtlib25.v 2009/02/13 Some updates.