EEC 180A - Digital Systems I
Fall 2009

Course Information

• Instructor
  Prof. Bevan Baas
  2037 Kemper Hall

  Teaching Assistants

  • Trevin Murakami, tmurakami(AT)ucdavis.edu
  • Calvin Chiem, cychiem(AT)ucdavis.edu
  • Richard Zhang, rszhang(AT)ucdavis.edu

  Office hours, in 2110 Kemper unless noted otherwise (tentative)

  	Mon	Tue	Wed	Thur	Fri
  Prof. Baas		10:30-11:30 am 176 Chem; 2037 Kemper	2:00-3:00 pm 2037 Kemper	10:30 am 176 Chem
  Trevin Murakami		2:00-3:00 pm 3-7 pm Lab		11:00-12:00 pm Kemper 2110
  Calvin Chiem			4:45-5:00 pm 5-9 pm Lab		1:00-2:00 pm
  Richard Zhang	10:30-11:30 am			1:45-2:00 pm 2-6 pm Lab

  
  Prof. Baas in 2037 Kemper and TAs in 2110 Kemper unless noted otherwise.

  Lecture

  TTh, 9:00 - 10:20am

  176 Chem

  Textbook

  Fundamentals of Logic Design

  C. H. Roth

  6th edition (although very similar to the 5th edition, the 6th has new homework problems)

  Download the text's errata

  Communication

  • Course web page:   http://www.ece.ucdavis.edu/~bbaas/180a/
  • Immediately after each lecture I will be available in the lecture room or right outside.
  • Instructor office hours.
  • TA office hours.
  • Email the TA for your lab section for urgent or personal matters that cannot be handled through office hours or during lab time.

  Grading

  • 10%   Weekly homework
  • 25%   Lab work (must be completed for course credit)
  • 10%   Quizzes
  • 20%   Midterm
  • 35%   Final

  Additional course information

  • Prerequisites: PHY 9C
  • The Roth text is sufficient for this course but if a second textbook is desired, I suggest: Contemporary Logic Design, Second edition, Randy H. Katz and G. Borriello, Pearson Prentice Hall, 2005.

Lab Information

Prelabs.   Except for Lab 1, prelabs are due at the beginning of the indicated lab section. They will be graded quickly on a scale from 0-5 points by your TA. The on-time deadline is 15 minutes after start of class. Unfortunately, points can not be given for the prelab portion after this time.

Lab checkoffs and lab reports are due at the beginning of the lab section the following week immediately after prelab checkoffs. (see Assignments table below.) Due to the large amount of grading for TAs, and because of the fast pace of material in lab, credit for late lab reports is not possible.

Lab checkoffs are graded on the following scale (note there is no 4):
    0   Little attempt made
    1   Not fully built
    2   All there, but not working
    3   Just about correct
    -   -
    5   Totally correct

Basic info

• Meets in 2110, Kemper Hall
• Logging into computers in room 2110 requires that you have a standard ECE account name and password, which you should have if you are enrolled in the course. If you have not logged into an ECE linux machine before, your username will be your UCD login name, and the password is as described in http://www.ece.ucdavis.edu/man/account/eceacct.html.
  To make sure the first lab goes smoothly, try to log in to a lab machine during open lab hours before your first lab. If you have a problem, see someone in computer support in rooms 2156/2158/2160.
• You must bring your own protoboards (a.k.a., solderless breadboards) and wire cutters to lab starting with Lab 2. Here is some more information.
• Lab grades will be adjusted so the average grade for each lab section will be the same.
• For several logistical reasons, only your section's TA can sign off your lab. I realize that is not the most convenient option for students, but it is necessary so TAs can focus on the students in their own section during labs. The only exception is that the TA present during a Saturday session may sign off only the circuit portions of labs.
• Written work may be done on any type of paper (though graph paper will generally produce a better result) and must be neat whether typed or hand-written. Bound lab books should not be used.
• You may go to another section and use the equipment only if there is space available. The students for that section have priority for the equipment and assistance from the TA. This is the priority for workstations in 2110 during lab times:
  1. Students enrolled in that lab section
  2. Students enrolled in that lab section that were on the wait list on the drop day
  3. Students enrolled in other lab sections
• In general, you are free to use the 2110 lab M-F 7am-7pm anytime a lab section is not using the room. The lab will normally be open Saturdays as well.
• If you wish to work at the open lab section on Saturdays, it should normally be open. If you will definitely be there on a particular Saturday and need TA help, notify your TA and if there is sufficient interest, a TA will be there for part of the 10am-6pm period.
• The TA will normally close up the lab and ask students to leave at the end of the 4-hour lab period (esp. the night labs).
• No food or drinks are allowed in the lab. Equipment is connected to an alarm system so be careful to not move equipment which will set off the alarm.

Downloads

• Lab report cover sheet
• Lab report requirements

Handouts and lab tips

• Tips for building and debugging your circuits
• Active high vs. active low
• How to use switches to generate digital inputs
• Using LEDs in lab (ppt)
• Lab circuit schematics - 3 types

Lab Sections and Teaching Assistants

• Section A01, Tue 3-7pm: TBD
• Section A02, Wed 5-9pm: TBD
• Section A03, Th 2-6pm: TBD
• Open times: Mon-Fri, most of the day 7am-7pm except when in use by other labs courses; Saturdays, 10am-6pm

Datasheets for parts used in lab

• 74194, Shift Registers
• 74LS00, quad 2-input NAND
• 74LS02, quad 2-input NOR
• 74LS04, hex INV
• 74LS10, triple 3-input NAND
• 74LS20, dual 4-input NAND
• 74LS47, BCD-to-seven-segment decoder/driver
• 74LS73A, dual J-K Flip-flops with clear
• 74LS74A, dual D pos-edge Flip-flops with preset and clear
• 74LS83A, 4-bit adder with carry
• 74LS125a, quad tri-state bus buffers
• 74LS153, dual 4:1 muxes
• 74LS163A, synchronous 4-bit counter
• 74LS245, octal tri-state bus transceiver
• 74LS257B, quad 2:1 muxes
• 74LS283, 4-bit adder with carry
• 74LS373, octal transparent latches
• 7-segment LED displays (both are active low, common anode, common Vcc; interchangeable and pin compatible): MAN72A, Kingbright SA03-12HDB, Fairchild 5082-7651
• DC10-EWA, 10-segment LED Bargraph
• Resistor SIP package
• CPLD documentation
  • Reference manual for the Digilent XC2-XL board
  • Schematic for the Digilent XC2-XL board
  • Xilinx CoolRunner-II CPLD Family Overview (XC2C256 detailed data sheet)
  • WebPack software tools
• No longer used in lab: GAL22V10, Generic Array Logic (GAL) chip

Course Policies

Homework

All work must be done individually. On each homework, write your name, lab section number, and problem set number clearly at the top.

All homeworks are due Friday at 4:00pm in Room 2131 and will be returned in your lab section after grading. Unfortunately, late homeworks cannot be accepted except for verifiable medical excuses approved by the instructor.

Each major portion of each problem will be graded on a three-point scale: 0 (not a full effort), 1 (close but fundamental problem), and 2 (correct).

Quizzes, Midterm, and Final exam

Three closed-book, closed-notes quizzes will be given throughout the quarter. They are designed such that students that keep up with material should earn high scores. Students that do not keep up with material will likely receive much lower scores. They will be announced in class one lecture before being given. The lowest of the three scores will be dropped. Unless stated otherwise, potential quiz topics include material covered up to and including the previous lecture, and generally emphasize material since the last quiz/midterm.

The midterm and final exam are mandatory components of this course. They are designed to test a working knowledge and understanding of concepts, not just mechanical procedures. Unfortunately, no early or late exams are possible. If an unavoidable emergency prevents your attendance at the midterm or final, you will be required to submit written proof of the emergency and the make-up exam will likely be given as an oral exam with the instructor.

Quizzes, the midterm, and the final exam will cover material from:

• Lectures,
• Assigned readings,
• Labs, and
• Homeworks.
Some material may be present in only one of these sources.

You may bring one page of double-sided hand-written (no photocopying) notes to the midterm and final.

The final exam is cumulative but with an emphasis on material since the midterm.

Grading Errors

Clear and significant grading errors should be described and justified in writing and given to the instructor within a week of being returned. Due to the inherent subjectiveness of grading and to be fair to all students, only truly significant mis-grades will result in a grade change. In addition to the description of the suspected grading error, you must write the following on your regrade request and sign immediately below it. "I certify that I have not altered this work in any way after it was returned to me. I understand that such altering would constitute a violation of the Code of Academic Conduct." Note that to discourage falsified regrading, some number of all graded assignments/labs/exams will be photocopied before being returned to students.

Individual work and Dishonesty

In this course, all work must be done "individually"--meaning done entirely by the student whose name is on the work. However, asking other students conceptual questions and explaining high-level concepts are important steps in the learning process and are strongly encouraged. This is very different from giving or receiving aid related to a specific assigned problem--which is not permitted. Copying someone else's work or allowing your work to be copied in any setting (hwk, lab, exams,...) does not promote learning, is unfair to honest students, and will be reported to Student Judicial Affairs. Students that observe inappropriate activity should report what they see (anonymously if desired) to a TA or the instructor.

Course Schedule

Date	Reading	Lecture	Slides	Notes
Th, Sept. 24	Unit 1	Course introduction, binary arithmetic, 2's complement review	Lecture01.pdf	Unit 1
Tue, Sept. 29	Unit 2	Boolean algebra: basic operators and theorems		Unit 2a Unit 2b
Th, Oct. 1	Unit 3 Unit 4	Boolean theorems cont'd; SOP, POS		Unit 3
Tue, Oct. 6	Unit 5	Minterms, maxterms, incompletely specified functions	Minterms.ppt	Unit 4 Unit 5
Th, Oct. 8		Karnaugh maps		Unit 5 Extra
Tue, Oct. 13	Unit 6	Implicants, Quine-McCluskey Method I		Unit 6
Th, Oct. 15	Unit 9.6	Quine-McCluskey II, PLDs		Unit 9.6 Handout: PLA example
Tue, Oct. 20	Unit 9	Muxes, tri-state		Unit 9 Unit 9, muxes II
Th, Oct. 22	Unit 7	Decoders, encoders, ROMs, FPGAs		Unit 7
Tue, Oct. 27	Unit 8	Multi-level circuits, NAND, NOR		Unit 8
Th, Oct. 29		Midterm 176 Chem:     A-Le 168 Hoagland: Li-Z
Tue, Nov. 3	Unit 11	Delays and hazards		Unit 11
Th, Nov. 5	Unit 4.7 Unit 12	Clockless latches, level-sensitive latches, flip-flops, Counters I		Unit 12 Handout: Adders
Tue, Nov. 10	Unit 13	Counters II, registers		Unit 13
Th, Nov. 12	Unit 14	Adders, accumulators, shift registers, Finite State Machine analysis: Moore		Unit 14
Tue, Nov. 17		FSMs: Mealy, Finite State Machine design, state assignments	CounterEx.ppt, pdf
Th, Nov. 19	Unit 15	Moore vs. Mealy, State simplification I		Unit 15
Tue, Nov. 24	Unit 16	State simplification II, Sequence detection		Unit 16
Th, Nov. 26		Happy Thanksgiving - no lecture
Tue, Dec. 1	Unit 18	Design example, state assignment guidelines		Unit 18
Th, Dec. 3		Critical timing relationships, fast adders Not covered in lecture: HDLs, multipliers, shifters		Handout: HDLs
Wed, Dec. 9 1-3pm		Final exam Wellman 106

Assignments

• Suggestion: beat the rush and get your design checked-off early!
• Suggestion: the fastest way to get a design working is to spend time debugging and testing with pencil and paper. Draw waveforms, think of test cases, and think through various modes with paper and pencil. Make sure you know exactly how each part works and be fairly confident of what is right even before you enter the design into the computer, much less start wiring it up on your board. I guarantee your understanding will be far greater, you will have a much greater chance of it working, and assuming it works, you will be done much sooner if you do this.
• Suggestion: carefully check your pin assignments and/or signal polarities (active high or low) before wiring it up on your board.
• Students may attend other sections in the 10th week and try to get their labs checked off but will have the lowest priority in terms of benches, TA time, and the FPGA board.