EEC 180A - Digital Systems I
Winter 2013

Course Information

Lab Information

Each lab has three major components: 1) the prelab, 2) the circuit/simulation work done in the lab, and 3) the lab report. The first two components must be signed off by your section's TA and your report must be turned in to your section's TA.

Prelabs.   Except for Lab 1, prelabs are due at the beginning of the indicated lab section. They will be graded quickly on a scale from 0-5 points by your TA. The on-time deadline is 15 minutes after start of class. Unfortunately, points can not be given for the prelab portion after this time.

Lab circuit checkoffs are due at the beginning of the lab section the following week immediately after prelab checkoffs (see Assignments table below). They are graded on the following scale (note there is no 4):
    0   Little attempt made
    1   Not fully built
    2   All there, but not working
    3   Just about correct
    -   -
    5   Totally correct

Lab reports are due at the same time as the lab circuit checkoffs. Due to the large amount of grading for TAs, and because of the fast pace of material in lab, credit for late lab reports is not possible.

Basic information

Lab reports

Tips for supporting circuits and good design practices

Datasheets for parts used in lab

Part counts of the standard design kit are shown in parentheses. A special thanks to Lance Halsted who developed or assisted in developing most of these labs.

Course Policies

Homework

Quizzes, Midterm, and Final exam

Grading Errors

Individual work and Dishonesty

Course Schedule

Future details are tentative.

Date Reading Lecture Slides Notes
Tue, Jan. 8 Unit 1 Course introduction, binary arithmetic, 2's complement review Lecture01 Unit 1
Th, Jan. 10 Unit 2 Boolean algebra: basic operators and theorems   Unit 2a
Unit 2b
Tue, Jan. 15 Unit 3
Unit 4
Boolean theorems cont'd; SOP, POS   Unit 3
Th, Jan. 17 Unit 5 Minterms, maxterms, incompletely specified functions Minterms.ppt, pdf Unit 4
Unit 5
Tue, Jan. 22   Karnaugh maps   Unit 5 Extra
Th, Jan. 24 Unit 6 Implicants, Quine-McCluskey Method I   Unit 6
Tue, Jan. 29 Unit 9.6 Quine-McCluskey II, PLDs   Unit 9.6
Handout: PLA example
Th, Jan. 31 Unit 9 Quiz 1
Muxes, tri-state
  Unit 9
Unit 9, muxes II
Tue, Feb. 5 Unit 7 Decoders, encoders, ROMs, FPGAs   Unit 7
Th, Feb. 7 Unit 8 Multi-level circuits, NAND, NOR   Unit 8
Handout: Adders
Tue, Feb. 12 Unit 11 Quiz 2
Delays and hazards
  Unit 11
Th, Feb. 14 Unit 4.7
Unit 12
Clockless latches, level-sensitive latches, flip-flops,
Counters I
  Unit 12
Tue, Feb. 19   Midterm
Covers Units 1-7, 9
Last name A-K: 55 Roessler
Last name L-Z: 176 Chem
   
Th, Feb. 21 Unit 13 Counters II, registers   Unit 13
Tue, Feb. 26 Unit 14 Adders, accumulators, shift registers, Finite State Machine analysis: Moore   Unit 14
Th, Feb. 28   FSMs: Mealy, Finite State Machine design, state assignments CounterEx.ppt, pdf  
Tue, Mar. 5 Unit 15 Quiz 3
Moore vs. Mealy, State simplification I
  Unit 15
Th, Mar. 7 Unit 16 State simplification II, Sequence detection   Unit 16
Tue, Mar. 12 Unit 18 Design example, state assignment guidelines, critical timing relationships,   Unit 18
Th, Mar. 14   HDLs,
fast adders, multipliers, shifters
  Handout: HDLs
Wed, Mar. 20
6-8pm
  Final exam
66 Roessler
   

Assignments

Week Prelab due and
work in Lab
Lab report due at
beginning of lab section
Hwk due
Friday 4pm
Homework problems
(Problems in italics have their solution in the textbook;
Problems in gray are tentative until approximately the Thurs 8 days
before the due date, depending on material covered in lecture)
Jan 8 - Jan 11 - - - -

Jan 14 - Jan 18 Lab 1 - 1 Unit 1: 1, 3, 4, 5 (do subt. by adding 2's comp), 7, 8, 35  
Unit 2: 1, 2, 4, 11ace, 13ac, 15b, 16a, 23bd, 25c, 26a
Jan 21 - Jan 25 Lab 2
Lab Instrument Tutorial
Scope Tutorial
Lab 1 2 Unit 2: 27, 29b
Unit 3: 1, 2, 3, 4, 5 (do not submit these five)
          9, 11, 15de, 16a, 17ad, 25ab,
Unit 4: 1a&b, 2b
Jan 28 - Feb 1 Lab 3 Lab 2 3 Unit 4: 3, 5, 16, 19, 24, 27, 35a
Unit 5: Study guide 1-8, 1, 2 (do not submit these ten)
          4, 8, 14abc, 19, 22fg, 28
Feb 4 - Feb 8 no new lab Lab 3 4 Unit 5: 26a, 32, 33
Unit 6: 1 (do not submit this one)
          2, 3, 16
Unit 9: 1, 4a, 8a, 14, 15, 19
Feb 11 - Feb 15 Lab 4 - 5 Unit 9: 20, 25, 27, 29 ("invalid" means "unrepresentable")
Unit 7: 1, 4, 21df
Feb 18 - Feb 22 Lab 5 Lab 4 6 Unit 7: 5, 27, 32, 39
Unit 8: 1, 2, 9, 10
Unit 11: 1, 2, 11
Feb 25 - Mar 1 Lab 6 Lab 5 7 Unit 11: 7, 14, 21
            29 (do not submit this one)
Unit 12: 3, 6, 7b, 8b, 30, 32
Unit 13: 1 (do not submit this one)
Mar 4 - Mar 8 Lab 7 Lab 6 8 Unit 13: 2, 3, 13, 17, 20, 24
Unit 14: 1, 2, 3 Programmed Exercises (submit all three)
Mar 11 - Mar 15 Lab 7 con't Lab 7 due
4 pm, Fri, Mar 15
in hwk box*
Late checkoff times:
Fri 12-1pm
Fri 1-2pm
Fri 2-3pm
9 Unit 14: 6, 8, 10, 13, 26
Unit 15: 3, 4, 9, 11, 20
Unit 16: 8, 20

* The later labs especially require a lot of time and you may run into design difficulties. To alleviate this problem, I have the following suggestions and must implement the following policies:


Recent changes, except information in the tables, will generally be colored green.