Project Title Asynchronous Design and Applications |
Funding
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Short Description Investigate
design, analysis, testing and synthesis of asynchronous circuits and systems.
Asynchronous Superscalar architecture and dynamic instructions scheduling |
Students
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Selected Publications á
T. Werner, V.
Akella. COUNTERFLOW PIPELINE
BASED DYNAMIC INSTRUCTION SCHEDULING. Proceedings of Second International Symposium on
Advanced Research in Asynchronous Circuits and Systems, pp. 69-79. á
T. Werner and V.
Akella. ASYNCHRONOUS PROCESSOR SURVEY.
IEEE Computer, Vol.
30, No. 11, pp. 67-76. á
K. Maheswar and V.
Akella,. PGA-STC: A PROGRAMMABLE
GATE ARRAY FOR SELF-TIMED CIRCUITS.
International Journal of Electronics, Vol. 84, No. 3, pp. 255-267 á
D. Johnson and V.
Akella. DESIGN AND ANALYSIS OF
ASYNCHRONOUS ADDER. IEE Proceedings for Computers and Digital
Techniques, Vol. 145, No. 1, pp.
1-8. á
D. Johnson, V.
Akella, and B. Stott. MICROPIPELINED SYNCHRONOUS DISCRETE COSINE TRANSFORM
(DCT/IDCT) PROCESSOR. IEEE Transactions on VLSI Systems, Vol. 6, No. 4, pp. 731-740. á
V. Akella, N. H.
Vaidya, and G. R. Redinbo. ASYNCHRONOUS
COMPARISON-BASED DECODERS FOR DELAY-INSENSITIVE CODES. IEEE
Transaction on Computers, Vo.
47, No. 7, pp. 802-811. á
N. Raghavan, V.
Akella, and S. Bakshi.
AUTOMATION INSERTION OF GATED CLOCKS AT REGISTER TRANSFER LEVEL. Proceedings of the Twelfth
International Conference on VLSI Design, IEEE Computer Society, pp. 48-54. á
T. Werner and V.
Akella. AN ASYNCHRONOUS SUPERSCALAR ARCHITECTURE FOR EXPLOITING
INSTRUCTION-LEVEL PARALLEISM. Proceedings of the International Symposium on
Advanced Research on Asynchronous Circuits and Systems, ASYNC 2001, March 2001, pp. 140-151. |