• Control FPGA ERS
  
  Information on Peripheral devices, etc...
• Measurement Board Control Script
  
  Perl script to control Measurement Board:

  • Configure AD9516 Clock Generator
  • Configure DAC5682Z 16-bit 1GS/s DAC
  • Read/Write Access to Data Path FPGA
  • Block RAM Waveform Upload to Data Path FPGA
  • Configuration of Data Path FPGA
  • LED Control
  • Temperature Sensor Read Back
  • More to come...

• Data Path FPGA ERS
  
  Information on Measurement Board, Signal Processing, FPGA, etc...
• Signal Source Data Path FPGA ERS
  
  Information on Signal Source FPGA, etc...

• Schematics: meas_main_board.pdf - Black and White.
• Schematics: meas_main_board.pdf - Color.
• Assembly Top Diagram
• Assembly Bottom Diagram
• Bill of Materials - Excel Spreadsheet
• Bill of Materials - Text File
• Virtex-5 IODELAY Adjustments:
• ADC IODELAY Taps
• DAC IODELAY Taps
• DDR2 SDRAM IODELAY Taps
• QDR-II SRAM IODELAY Taps
• AsAPV2 No. 1 IODELAY Taps
• AsAPV2 No. 2 IODELAY Taps
• P342 PCB Top View Picture
• AsAPv2 PCB Location Top View Picture

• Schematics: sodimm_interposer.pdf - Black and White.
• Schematics: sodimm_interposer.pdf - Color.
• Assembly Top Diagram
• Assembly Bottom Diagram
• Bill of Materials - Text File

• Front Panel Graphics
• Rear Panel Graphics

• Measurement Results
• Measurement Board Turn-On Notes

• Multipurpose Baseband Instrument Slideset

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• 
  
  We gratefully acknowledge Xilinx's generous donation of the Virtex-5 SX50T (XC5VSX50T-2FFG1136C) FPGAs.
• and
  
  We gratefully acknowledge the donation of 50 licenses for both Synplify Premier and Synplify DSP from Synopsys.

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Jeremy W. Webb

Graduate Student

Electrical and Computer Engineering Department

One Shields Avenue

Davis, CA 95616

Last Modified: Saturday, October 31, 2009 10:58:30 AM