Today is: Tuesday November 24, 2009
This site contains information on my Master's Thesis Measurement Board design.
Measurement Board Information:
- Measurement Board ERS
Information on Measurement Board, Signal Processing, FPGA Pinouts, etc...
- Control FPGA ERS
Information on Peripheral devices, etc...
- Signal Source Data Path FPGA ERS
Information on Signal Source FPGA, etc...
Presentations:
Measurement Board (p342):
- Schematics: meas_main_board.pdf - Black and White.
- Schematics: meas_main_board.pdf - Color.
- Assembly Top Diagram
- Assembly Bottom Diagram
- Bill of Materials - Excel Spreadsheet
- Bill of Materials - Text File
- Virtex-5 IODELAY Adjustments:
- ADC IODELAY Taps
- DAC IODELAY Taps
- DDR2 SDRAM IODELAY Taps
- QDR-II SRAM IODELAY Taps
- AsAPV2 No. 1 IODELAY Taps
- AsAPV2 No. 2 IODELAY Taps
- P342 PCB Top View Picture
- AsAPv2 PCB Location Top View Picture
SODIMM Interposer Board (p389):
- Schematics: sodimm_interposer.pdf - Black and White.
- Schematics: sodimm_interposer.pdf - Color.
- Assembly Top Diagram
- Assembly Bottom Diagram
- Bill of Materials - Text File
Chassis:
Donations:
-
We gratefully acknowledge Xilinx's generous donation of the Virtex-5 SX50T (XC5VSX50T-2FFG1136C) FPGAs. -
and 
We gratefully acknowledge the donation of 50 licenses for both Synplify Premier and Synplify DSP from Synopsys.
Jeremy W. Webb Graduate Student Electrical and Computer Engineering Department One Shields Avenue Davis, CA 95616
Last Modified: Saturday, November 21, 2009 02:44:53 PM
