# -------------------------------------------------------------
#   Copyright(C) 2005-2006 by Xilinx, Inc. All rights reserved.   --
#                                                            --
#   This copyright notice must be retained as part           --
#   of this text at all times.                               --
# -------------------------------------------------------------

ATTRIBUTE VENDOR = UC Davis
ATTRIBUTE SPEC_URL = http://www.centellax.com
ATTRIBUTE CONTACT_INFO_URL = http://www.xilinx.com/support/techsup/tappinfo.htm
ATTRIBUTE NAME = Measurement Board - Spartan 3A XC3S1400A
ATTRIBUTE REVISION = A
ATTRIBUTE DESC = Measurement Board Revision 1
ATTRIBUTE LONG_DESC = 'The Measurement Board utilizes Xilinx Spartan-3A XC3S1400A-4FG484 device. The board includes 1 RS232 serial ports, 4 DIP switches, 6 push buttons, 8 LEDs, SPI analog to digital converter, SPI digital to analog converter, 64Mb SPI flash, 512 Mb DDR SDRAM. Push button South(RESET) is used as system reset. '

# Clock Input
BEGIN IO_INTERFACE
 ATTRIBUTE IOTYPE = XIL_CLOCK_V1
  ATTRIBUTE INSTANCE =clk_10
  PARAMETER CLK_FREQ =10000000, IO_IS=clk_freq, RANGE=(10000000)   # 10 Mhz
  PORT FPGA.CLK_P = CONN_CLK_P, IO_IS=int_clk_p
  PORT FPGA.CLK_N = CONN_CLK_N, IO_IS=int_clk_n
END

# Reset Input
BEGIN IO_INTERFACE
  ATTRIBUTE IOTYPE = XIL_RESET_V1
   ATTRIBUTE INSTANCE =rst_0
   PARAMETER RST_POLARITY =0, IO_IS=polarity, VALUE_NOTE=Active Low
   PORT FPGA.RESET = CONN_FPGA.RESET, IO_IS=ext_rst
END

# CP2102 USB-to-RS232 Bridge
BEGIN IO_INTERFACE
  ATTRIBUTE IOTYPE = XIL_UART_V1
   ATTRIBUTE INSTANCE=RS232_CP2102
   PORT RXD_CP2102 = CONN_RXD_CP2102, IO_IS=serial_in
   PORT TXD_CP2102 = CONN_TXD_CP2102, IO_IS=serial_out, INITIALVAL = GND
END    

# 8 LEDs
BEGIN IO_INTERFACE
   ATTRIBUTE IOTYPE = XIL_GPIO_V1
   ATTRIBUTE INSTANCE = LEDs_8Bit
   PARAMETER num_bits =8, IO_IS=num_bits
   PARAMETER is_dual=0, IO_IS=is_dual 
   PARAMETER bidir_data=0, IO_IS=is_bidir     # Non-bidir data pins
   PARAMETER all_inputs =0, IO_IS=all_inputs   # All outputs
   PORT LED7 = CONN_LED7, IO_IS = gpio_data_out[0], INITIALVAL = VCC
   PORT LED6 = CONN_LED6, IO_IS = gpio_data_out[1], INITIALVAL = VCC
   PORT LED5 = CONN_LED5, IO_IS = gpio_data_out[2], INITIALVAL = VCC
   PORT LED4 = CONN_LED4, IO_IS = gpio_data_out[3], INITIALVAL = VCC
   PORT LED3 = CONN_LED3, IO_IS = gpio_data_out[4], INITIALVAL = VCC
   PORT LED2 = CONN_LED2, IO_IS = gpio_data_out[5], INITIALVAL = VCC
   PORT LED1 = CONN_LED1, IO_IS = gpio_data_out[6], INITIALVAL = VCC 
   PORT LED0 = CONN_LED0, IO_IS = gpio_data_out[7], INITIALVAL = VCC  
END       

# 4 pin DIP Switch
BEGIN IO_INTERFACE
  ATTRIBUTE IOTYPE = XIL_GPIO_V1
   ATTRIBUTE INSTANCE = DIP_Switches_4Bit
   PARAMETER num_bits =4, IO_IS=num_bits
   PARAMETER is_dual=0, IO_IS=is_dual 
   PARAMETER bidir_data=0, IO_IS=is_bidir     # Non-bidir data pins
   PARAMETER all_inputs=1, IO_IS=all_inputs   # All inputs
   
   PORT DIP1 = CONN_DIP1, IO_IS = gpio_data_in[0]
   PORT DIP2 = CONN_DIP2, IO_IS = gpio_data_in[1]
   PORT DIP3 = CONN_DIP3, IO_IS = gpio_data_in[2]
   PORT DIP4 = CONN_DIP4, IO_IS = gpio_data_in[3]
END       

# 6 Push-Buttons (Active Low)
BEGIN IO_INTERFACE
  ATTRIBUTE IOTYPE = XIL_GPIO_V1
   ATTRIBUTE INSTANCE = Buttons_6Bit
   PARAMETER num_bits =6, IO_IS=num_bits
   PARAMETER is_dual=0, IO_IS=is_dual 
   PARAMETER bidir_data=0, IO_IS=is_bidir     # Non-bidir data pins
   PARAMETER all_inputs=1, IO_IS=all_inputs   # All inputs
   PORT BUT1 = CONN_BUT1, IO_IS = gpio_data_in[0]
   PORT BUT2 = CONN_BUT2, IO_IS = gpio_data_in[1]
   PORT BUT3 = CONN_BUT3, IO_IS = gpio_data_in[2]
   PORT BUT4 = CONN_BUT4, IO_IS = gpio_data_in[3]
   PORT BUT5 = CONN_BUT5, IO_IS = gpio_data_in[4]
   PORT BUT6 = CONN_BUT6, IO_IS = gpio_data_in[5]
END  

# M25P64 SPI Flash 64Mb
BEGIN IO_INTERFACE
   ATTRIBUTE IOTYPE = XIL_SPI_V1
   ATTRIBUTE INSTANCE = SPI_FLASH
   PARAMETER C_SCK_RATIO=32, IO_IS=clk_freq
   PARAMETER C_BASEADDR=0x00000000, IO_IS=C_BASEADDR
   PARAMETER C_BASEADDR=0x0000ffff, IO_IS=C_HIGHADDR			 
   PARAMETER C_NUM_OFFCHIP_SS_BITS=1, IO_IS=offchip_ss_bits
   PARAMETER C_NUM_SS_BITS=1, IO_IS=ss_bits
   PARAMETER C_FIFO_EXIST=1, IO_IS=fifo_exist
   PORT SPISEL= net_vcc
   PORT MISO=spi_MISO, IO_IS=data_out
   PORT MOSI=spi_MOSI, IO_IS=data_in
   PORT SCK=spi_SCK, IO_IS=clk_out
   PORT SS=spi_cs, IO_IS=chip_select
END  

# User Interface Board SPI Port
BEGIN IO_INTERFACE
 ATTRIBUTE IOTYPE = XIL_SPI_V1
 ATTRIBUTE INSTANCE = SPI_UI
 PARAMETER C_FIFO_EXIST = 1, IO_IS=fifo_exist
 PARAMETER C_SCK_RATIO = 32, IO_IS=clk_freq
 PARAMETER C_NUM_OFFCHIP_SS_BITS = 1
 PARAMETER C_NUM_SS_BITS = 1
 PARAMETER C_BASEADDR = 0x00000000, IO_IS=C_BASEADDR
 PARAMETER C_BASEADDR = 0x0000ffff, IO_IS=C_HIGHADDR
 PORT SPISEL = net_vcc
 PORT UI_MISO = fpga_0_SPI_UI_MISO, IO_IS=data_out
 PORT UI_MOSI = fpga_0_SPI_UI_MOSI, IO_IS=data_in
 PORT UI_SCK = fpga_0_SPI_UI_SCK,   IO_IS=clk_out
 PORT UI_SS = fpga_0_SPI_UI_SS,     IO_IS=chip_select
END

# microSD Card 2GB
BEGIN IO_INTERFACE
 ATTRIBUTE IOTYPE = XIL_SPI_V1
 ATTRIBUTE INSTANCE = SPI_SD
 PARAMETER C_FIFO_EXIST = 1, IO_IS=fifo_exist
 PARAMETER C_SCK_RATIO = 32, IO_IS=clk_freq
 PARAMETER C_NUM_OFFCHIP_SS_BITS = 1
 PARAMETER C_NUM_SS_BITS = 1
 PARAMETER C_BASEADDR = 0x00000000, IO_IS=C_BASEADDR
 PARAMETER C_BASEADDR = 0x0000ffff, IO_IS=C_HIGHADDR
 PORT SPISEL = net_vcc
 PORT SD_MISO = fpga_0_SPI_SD_MISO, IO_IS=data_out
 PORT SD_MOSI = fpga_0_SPI_SD_MOSI, IO_IS=data_in
 PORT SD_SCK = fpga_0_SPI_SD_SCK,   IO_IS=clk_out
 PORT SD_SS = fpga_0_SPI_SD_SS,     IO_IS=chip_select
END

# AD7923 Octal 12-bit ADC
BEGIN IO_INTERFACE
 ATTRIBUTE IOTYPE = XIL_SPI_V1
 ATTRIBUTE INSTANCE = SPI_ADC
 PARAMETER C_FIFO_EXIST = 1, IO_IS=fifo_exist
 PARAMETER C_SCK_RATIO = 32, IO_IS=clk_freq
 PARAMETER C_NUM_OFFCHIP_SS_BITS = 1
 PARAMETER C_NUM_SS_BITS = 1
 PARAMETER C_BASEADDR = 0x00000000, IO_IS=C_BASEADDR
 PARAMETER C_BASEADDR = 0x0000ffff, IO_IS=C_HIGHADDR
 PORT SPISEL = net_vcc
 PORT ADC_MISO = fpga_0_SPI_ADC_MISO, IO_IS=data_out
 PORT ADC_MOSI = fpga_0_SPI_ADC_MOSI, IO_IS=data_in
 PORT ADC_SCK = fpga_0_SPI_ADC_SCK,   IO_IS=clk_out
 PORT ADC_SS = fpga_0_SPI_ADC_SS,     IO_IS=chip_select
END

# AD5318 Octal 10-bit DAC
BEGIN IO_INTERFACE
 ATTRIBUTE IOTYPE = XIL_SPI_V1
 ATTRIBUTE INSTANCE = SPI_DAC
 PARAMETER C_FIFO_EXIST = 1, IO_IS=fifo_exist
 PARAMETER C_SCK_RATIO = 32, IO_IS=clk_freq
 PARAMETER C_NUM_OFFCHIP_SS_BITS = 1
 PARAMETER C_NUM_SS_BITS = 1
 PARAMETER C_BASEADDR = 0x00000000, IO_IS=C_BASEADDR
 PARAMETER C_BASEADDR = 0x0000ffff, IO_IS=C_HIGHADDR
 PORT SPISEL = net_vcc
 PORT DAC_MOSI = fpga_0_SPI_DAC_MOSI, IO_IS=data_in
 PORT DAC_SCK = fpga_0_SPI_DAC_SCK,   IO_IS=clk_out
 PORT DAC_SS = fpga_0_SPI_DAC_SS,     IO_IS=chip_select
END

# AD9958 DDS IC
BEGIN IO_INTERFACE
 ATTRIBUTE IOTYPE = XIL_SPI_V1
 ATTRIBUTE INSTANCE = SPI_DDS
 PARAMETER C_FIFO_EXIST = 1, IO_IS=fifo_exist
 PARAMETER C_SCK_RATIO = 32, IO_IS=clk_freq
 PARAMETER C_NUM_OFFCHIP_SS_BITS = 1
 PARAMETER C_NUM_SS_BITS = 1
 PARAMETER C_BASEADDR = 0x00000000, IO_IS=C_BASEADDR
 PARAMETER C_BASEADDR = 0x0000ffff, IO_IS=C_HIGHADDR
 PORT SPISEL = net_vcc
 PORT DDS_MISO = fpga_0_SPI_DDS_MISO, IO_IS=data_out
 PORT DDS_MOSI = fpga_0_SPI_DDS_MOSI, IO_IS=data_in
 PORT DDS_SCK = fpga_0_SPI_DDS_SCK,   IO_IS=clk_out
 PORT DDS_SS = fpga_0_SPI_DDS_SS,     IO_IS=chip_select
END

# AD9516 Clock Generator IC
BEGIN IO_INTERFACE
 ATTRIBUTE IOTYPE = XIL_SPI_V1
 ATTRIBUTE INSTANCE = SPI_CLKGEN
 PARAMETER C_FIFO_EXIST = 1, IO_IS=fifo_exist
 PARAMETER C_SCK_RATIO = 32, IO_IS=clk_freq
 PARAMETER C_NUM_OFFCHIP_SS_BITS = 1
 PARAMETER C_NUM_SS_BITS = 1
 PARAMETER C_BASEADDR = 0x00000000, IO_IS=C_BASEADDR
 PARAMETER C_BASEADDR = 0x0000ffff, IO_IS=C_HIGHADDR
 PORT SPISEL = net_vcc
 PORT CLKGEN_MISO = fpga_0_SPI_CLKGEN_MISO, IO_IS=data_out
 PORT CLKGEN_MOSI = fpga_0_SPI_CLKGEN_MOSI, IO_IS=data_in
 PORT CLKGEN_SCK = fpga_0_SPI_CLKGEN_SCK,   IO_IS=clk_out
 PORT CLKGEN_SS = fpga_0_SPI_CLKGEN_SS,     IO_IS=chip_select
END

# ADF4108 PLL CH A IC
BEGIN IO_INTERFACE
 ATTRIBUTE IOTYPE = XIL_SPI_V1
 ATTRIBUTE INSTANCE = SPI_PLL_CHA
 PARAMETER C_FIFO_EXIST = 1, IO_IS=fifo_exist
 PARAMETER C_SCK_RATIO = 32, IO_IS=clk_freq
 PARAMETER C_NUM_OFFCHIP_SS_BITS = 1
 PARAMETER C_NUM_SS_BITS = 1
 PARAMETER C_BASEADDR = 0x00000000, IO_IS=C_BASEADDR
 PARAMETER C_BASEADDR = 0x0000ffff, IO_IS=C_HIGHADDR
 PORT SPISEL = net_vcc
 PORT PLL_CHA_MISO = fpga_0_SPI_PLL_CHA_MISO, IO_IS=data_out
 PORT PLL_CHA_MOSI = fpga_0_SPI_PLL_CHA_MOSI, IO_IS=data_in
 PORT PLL_CHA_SCK = fpga_0_SPI_PLL_CHA_SCK,   IO_IS=clk_out
 PORT PLL_CHA_SS = fpga_0_SPI_PLL_CHA_SS,     IO_IS=chip_select
END

# ADF4108 PLL CH B IC
BEGIN IO_INTERFACE
 ATTRIBUTE IOTYPE = XIL_SPI_V1
 ATTRIBUTE INSTANCE = SPI_PLL_CHB
 PARAMETER C_FIFO_EXIST = 1, IO_IS=fifo_exist
 PARAMETER C_SCK_RATIO = 32, IO_IS=clk_freq
 PARAMETER C_NUM_OFFCHIP_SS_BITS = 1
 PARAMETER C_NUM_SS_BITS = 1
 PARAMETER C_BASEADDR = 0x00000000, IO_IS=C_BASEADDR
 PARAMETER C_BASEADDR = 0x0000ffff, IO_IS=C_HIGHADDR
 PORT SPISEL = net_vcc
 PORT PLL_CHB_MISO = fpga_0_SPI_PLL_CHB_MISO, IO_IS=data_out
 PORT PLL_CHB_MOSI = fpga_0_SPI_PLL_CHB_MOSI, IO_IS=data_in
 PORT PLL_CHB_SCK = fpga_0_SPI_PLL_CHB_SCK,   IO_IS=clk_out
 PORT PLL_CHB_SS = fpga_0_SPI_PLL_CHB_SS,     IO_IS=chip_select
END

# ADF4108 PLL RF IC
BEGIN IO_INTERFACE
 ATTRIBUTE IOTYPE = XIL_SPI_V1
 ATTRIBUTE INSTANCE = SPI_PLL_RF
 PARAMETER C_FIFO_EXIST = 1, IO_IS=fifo_exist
 PARAMETER C_SCK_RATIO = 32, IO_IS=clk_freq
 PARAMETER C_NUM_OFFCHIP_SS_BITS = 1
 PARAMETER C_NUM_SS_BITS = 1
 PARAMETER C_BASEADDR = 0x00000000, IO_IS=C_BASEADDR
 PARAMETER C_BASEADDR = 0x0000ffff, IO_IS=C_HIGHADDR
 PORT SPISEL = net_vcc
 PORT PLL_RF_MISO = fpga_0_SPI_PLL_RF_MISO, IO_IS=data_out
 PORT PLL_RF_MOSI = fpga_0_SPI_PLL_RF_MOSI, IO_IS=data_in
 PORT PLL_RF_SCK = fpga_0_SPI_PLL_RF_SCK,   IO_IS=clk_out
 PORT PLL_RF_SS = fpga_0_SPI_PLL_RF_SS,     IO_IS=chip_select
END

# UXN14M9P Clock Divider IC
BEGIN IO_INTERFACE
  ATTRIBUTE IOTYPE = XIL_GPIO_V1
  ATTRIBUTE INSTANCE = UXN14M9P_CLKDIV
   PARAMETER num_bits =9, IO_IS=num_bits
   PARAMETER is_dual=0, IO_IS=is_dual 
   PARAMETER bidir_data=0, IO_IS=is_bidir     # Non-bidir data pins
   PARAMETER all_inputs =0, IO_IS=all_inputs   # All outputs
   PORT CLK_DIV_SEL8 = CONN_CLK_DIV_SEL8, IO_IS = gpio_data_out[0], INITIALVAL = VCC
   PORT CLK_DIV_SEL7 = CONN_CLK_DIV_SEL7, IO_IS = gpio_data_out[1], INITIALVAL = VCC
   PORT CLK_DIV_SEL6 = CONN_CLK_DIV_SEL6, IO_IS = gpio_data_out[2], INITIALVAL = VCC
   PORT CLK_DIV_SEL5 = CONN_CLK_DIV_SEL5, IO_IS = gpio_data_out[3], INITIALVAL = VCC
   PORT CLK_DIV_SEL4 = CONN_CLK_DIV_SEL4, IO_IS = gpio_data_out[4], INITIALVAL = VCC
   PORT CLK_DIV_SEL3 = CONN_CLK_DIV_SEL3, IO_IS = gpio_data_out[5], INITIALVAL = VCC
   PORT CLK_DIV_SEL2 = CONN_CLK_DIV_SEL2, IO_IS = gpio_data_out[6], INITIALVAL = VCC 
   PORT CLK_DIV_SEL1 = CONN_CLK_DIV_SEL1, IO_IS = gpio_data_out[7], INITIALVAL = VCC  
   PORT CLK_DIV_SEL0 = CONN_CLK_DIV_SEL0, IO_IS = gpio_data_out[8], INITIALVAL = VCC  
END       

# UXD20P Prescaler IC
BEGIN IO_INTERFACE
  ATTRIBUTE IOTYPE = XIL_GPIO_V1
  ATTRIBUTE INSTANCE = UXD20P_PRESCALER
   PARAMETER num_bits =2, IO_IS=num_bits
   PARAMETER is_dual=0, IO_IS=is_dual 
   PARAMETER bidir_data=0, IO_IS=is_bidir     # Non-bidir data pins
   PARAMETER all_inputs =0, IO_IS=all_inputs   # All outputs
   PORT CLK_DIV_PRE1 = CONN_CLK_DIV_PRE1, IO_IS = gpio_data_out[0], INITIALVAL = VCC
   PORT CLK_DIV_PRE0 = CONN_CLK_DIV_PRE0, IO_IS = gpio_data_out[1], INITIALVAL = VCC
END       

# PE4309 Attenuator Channel A No. 1 IC
BEGIN IO_INTERFACE
  ATTRIBUTE IOTYPE = XIL_GPIO_V1
  ATTRIBUTE INSTANCE = PE4309_CHA_No1
   PARAMETER num_bits =6, IO_IS=num_bits
   PARAMETER is_dual=0, IO_IS=is_dual 
   PARAMETER bidir_data=0, IO_IS=is_bidir     # Non-bidir data pins
   PARAMETER all_inputs =0, IO_IS=all_inputs   # All outputs
   PORT PE4309_CHA1_CTRL5 = CONN_PE4309_CHA1_CTRL5, IO_IS = gpio_data_out[0], INITIALVAL = VCC
   PORT PE4309_CHA1_CTRL4 = CONN_PE4309_CHA1_CTRL4, IO_IS = gpio_data_out[1], INITIALVAL = VCC
   PORT PE4309_CHA1_CTRL3 = CONN_PE4309_CHA1_CTRL3, IO_IS = gpio_data_out[2], INITIALVAL = VCC
   PORT PE4309_CHA1_CTRL2 = CONN_PE4309_CHA1_CTRL2, IO_IS = gpio_data_out[3], INITIALVAL = VCC
   PORT PE4309_CHA1_CTRL1 = CONN_PE4309_CHA1_CTRL1, IO_IS = gpio_data_out[4], INITIALVAL = VCC
   PORT PE4309_CHA1_CTRL0 = CONN_PE4309_CHA1_CTRL0, IO_IS = gpio_data_out[5], INITIALVAL = VCC
END       

# PE4309 Attenuator Channel A No. 2 IC
BEGIN IO_INTERFACE
  ATTRIBUTE IOTYPE = XIL_GPIO_V1
  ATTRIBUTE INSTANCE = PE4309_CHA_No2
   PARAMETER num_bits =6, IO_IS=num_bits
   PARAMETER is_dual=0, IO_IS=is_dual 
   PARAMETER bidir_data=0, IO_IS=is_bidir     # Non-bidir data pins
   PARAMETER all_inputs =0, IO_IS=all_inputs   # All outputs
   PORT PE4309_CHA2_CTRL5 = CONN_PE4309_CHA2_CTRL5, IO_IS = gpio_data_out[0], INITIALVAL = VCC
   PORT PE4309_CHA2_CTRL4 = CONN_PE4309_CHA2_CTRL4, IO_IS = gpio_data_out[1], INITIALVAL = VCC
   PORT PE4309_CHA2_CTRL3 = CONN_PE4309_CHA2_CTRL3, IO_IS = gpio_data_out[2], INITIALVAL = VCC
   PORT PE4309_CHA2_CTRL2 = CONN_PE4309_CHA2_CTRL2, IO_IS = gpio_data_out[3], INITIALVAL = VCC
   PORT PE4309_CHA2_CTRL1 = CONN_PE4309_CHA2_CTRL1, IO_IS = gpio_data_out[4], INITIALVAL = VCC
   PORT PE4309_CHA2_CTRL0 = CONN_PE4309_CHA2_CTRL0, IO_IS = gpio_data_out[5], INITIALVAL = VCC
END       

# PE4309 Attenuator Channel B No. 1 IC
BEGIN IO_INTERFACE
  ATTRIBUTE IOTYPE = XIL_GPIO_V1
  ATTRIBUTE INSTANCE = PE4309_CHB_No1
   PARAMETER num_bits =6, IO_IS=num_bits
   PARAMETER is_dual=0, IO_IS=is_dual 
   PARAMETER bidir_data=0, IO_IS=is_bidir     # Non-bidir data pins
   PARAMETER all_inputs =0, IO_IS=all_inputs   # All outputs
   PORT PE4309_CHB1_CTRL5 = CONN_PE4309_CHB1_CTRL5, IO_IS = gpio_data_out[0], INITIALVAL = VCC
   PORT PE4309_CHB1_CTRL4 = CONN_PE4309_CHB1_CTRL4, IO_IS = gpio_data_out[1], INITIALVAL = VCC
   PORT PE4309_CHB1_CTRL3 = CONN_PE4309_CHB1_CTRL3, IO_IS = gpio_data_out[2], INITIALVAL = VCC
   PORT PE4309_CHB1_CTRL2 = CONN_PE4309_CHB1_CTRL2, IO_IS = gpio_data_out[3], INITIALVAL = VCC
   PORT PE4309_CHB1_CTRL1 = CONN_PE4309_CHB1_CTRL1, IO_IS = gpio_data_out[4], INITIALVAL = VCC
   PORT PE4309_CHB1_CTRL0 = CONN_PE4309_CHB1_CTRL0, IO_IS = gpio_data_out[5], INITIALVAL = VCC
END       

# PE4309 Attenuator Channel B No. 2 IC
BEGIN IO_INTERFACE
  ATTRIBUTE IOTYPE = XIL_GPIO_V1
  ATTRIBUTE INSTANCE = PE4309_CHB_No2
   PARAMETER num_bits =6, IO_IS=num_bits
   PARAMETER is_dual=0, IO_IS=is_dual 
   PARAMETER bidir_data=0, IO_IS=is_bidir     # Non-bidir data pins
   PARAMETER all_inputs =0, IO_IS=all_inputs   # All outputs
   PORT PE4309_CHB2_CTRL5 = CONN_PE4309_CHB2_CTRL5, IO_IS = gpio_data_out[0], INITIALVAL = VCC
   PORT PE4309_CHB2_CTRL4 = CONN_PE4309_CHB2_CTRL4, IO_IS = gpio_data_out[1], INITIALVAL = VCC
   PORT PE4309_CHB2_CTRL3 = CONN_PE4309_CHB2_CTRL3, IO_IS = gpio_data_out[2], INITIALVAL = VCC
   PORT PE4309_CHB2_CTRL2 = CONN_PE4309_CHB2_CTRL2, IO_IS = gpio_data_out[3], INITIALVAL = VCC
   PORT PE4309_CHB2_CTRL1 = CONN_PE4309_CHB2_CTRL1, IO_IS = gpio_data_out[4], INITIALVAL = VCC
   PORT PE4309_CHB2_CTRL0 = CONN_PE4309_CHB2_CTRL0, IO_IS = gpio_data_out[5], INITIALVAL = VCC
END       

BEGIN IO_INTERFACE
 ATTRIBUTE INSTANCE = clock_generator_0
 PARAMETER C_EXT_RESET_HIGH = 1
 PARAMETER C_CLKIN_FREQ = 10000000
 PARAMETER C_CLKOUT0_FREQ = 10000000
 PARAMETER C_CLKOUT0_PHASE = 0
 PARAMETER C_CLKOUT0_GROUP = NONE
 PARAMETER C_CLKOUT1_FREQ = 100000000
 PARAMETER C_CLKOUT1_PHASE = 0
 PARAMETER C_CLKOUT1_GROUP = GROUP0
 PARAMETER C_CLKOUT2_FREQ = 100000000
 PARAMETER C_CLKOUT2_PHASE = 90
 PARAMETER C_CLKOUT2_GROUP = GROUP0
 PORT CLKOUT0 = sys_clk_s
 PORT CLKOUT1 = DDR_SDRAM_mpmc_clk_s
 PORT CLKOUT2 = DDR_SDRAM_mpmc_clk_90_s
 PORT CLKIN = dcm_clk_s
 PORT LOCKED = Dcm_all_locked
 PORT RST = net_gnd
END

#BEGIN IO_INTERFACE
#  ATTRIBUTE IOTYPE = XIL_SPI_V1
#   ATTRIBUTE INSTANCE = SPI_SD
#   ATTRIBUTE EXCLUSIVE = FLASH
#   PARAMETER C_OPB_SCK_RATIO=32, IO_IS=clk_freq
#   PARAMETER C_BASEADDR=0x00000000, IO_IS=C_BASEADDR
#   PARAMETER C_BASEADDR=0x0000007f, IO_IS=C_HIGHADDR			 
#   PARAMETER C_NUM_OFFCHIP_SS_BITS=1, IO_IS=offchip_ss_bits
#   PARAMETER C_NUM_SS_BITS=1, IO_IS=ss_bits
#   PARAMETER C_FIFO_EXIST=1, IO_IS=fifo_exist
#   PORT SPISEL= net_vcc
#   PORT MISO=spi_MISO, IO_IS=data_out
#   PORT MOSI=spi_MOSI, IO_IS=data_in
#   PORT SCK=spi_SCK, IO_IS=clk_out
#   PORT SS0=spi_cs_0_, IO_IS=chip_select
#END  

# Uses Micron device 
BEGIN IO_INTERFACE
  ATTRIBUTE IOTYPE       = XIL_MEMORY_V1
  ATTRIBUTE INSTANCE     = DDR_SDRAM
  PARAMETER C_MEM_PARTNO = "MT46V32M16-6", IO_IS=C_MEM_PARTNO
  PARAMETER C_BASEADDR   = 0x00000000, IO_IS = C_BASEADDR, SHORT_DESC=DDR_SDRAM
  PARAMETER C_HIGHADDR   = 0x03FFFFFF, IO_IS = C_HIGHADDR
  PARAMETER C_SPECIAL_BOARD = S3E_1600E, IO_IS = C_SPECIAL_BOARD
  PARAMETER C_MEM_DATA_WIDTH  = 16,  IO_IS = C_MEM_DATA_WIDTH
  PARAMETER C_MEM_DQS_WIDTH   = 2,   IO_IS = C_MEM_DQS_WIDTH
  PARAMETER C_MEM_DM_WIDTH    = 2,   IO_IS = C_MEM_DM_WIDTH
  PARAMETER C_MEM_TYPE        = DDR, IO_IS = C_MEM_TYPE

  PORT DDR_FPGA_CK   = ddr_clk,     IO_IS = ddr_clk
  PORT DDR_Clk_n     = ddr_clk_n,   IO_IS = ddr_clk_n

  PORT A0   = ddr_addr_0_,  IO_IS = ddr_address[0]
  PORT A1   = ddr_addr_1_,  IO_IS = ddr_address[1]
  PORT A2   = ddr_addr_2_,  IO_IS = ddr_address[2]
  PORT A3   = ddr_addr_3_,  IO_IS = ddr_address[3]
  PORT A4   = ddr_addr_4_,  IO_IS = ddr_address[4]
  PORT A5   = ddr_addr_5_,  IO_IS = ddr_address[5]
  PORT A6   = ddr_addr_6_,  IO_IS = ddr_address[6]
  PORT A7   = ddr_addr_7_,  IO_IS = ddr_address[7]
  PORT A8   = ddr_addr_8_,  IO_IS = ddr_address[8]
  PORT A9   = ddr_addr_9_,  IO_IS = ddr_address[9]
  PORT A10  = ddr_addr_10_, IO_IS = ddr_address[10]
  PORT A11  = ddr_addr_11_, IO_IS = ddr_address[11]
  PORT A12  = ddr_addr_12_, IO_IS = ddr_address[12]

  PORT BS0  = ddr_ba_0_,    IO_IS = ddr_bankaddr[0]
  PORT BS1  = ddr_ba_1_,    IO_IS = ddr_bankaddr[1]

  PORT CASn = ddr_cas_n,    IO_IS = ddr_col_addr_select
  PORT CKE  = ddr_cke,      IO_IS = ddr_clock_enable
  PORT CSn  = ddr_cs_n,     IO_IS = ddr_chip_select
  PORT RASn = ddr_ras_n,    IO_IS = ddr_row_addr_select
  PORT WEn  = ddr_we_n,     IO_IS = ddr_write_enable
  # Point-to-point connections for data pins from FPGA to DDR SDRAM devices

  PORT LDM  = ddr_dm_0_,    IO_IS = ddr_data_mask[0]
  PORT UDM  = ddr_dm_1_,    IO_IS = ddr_data_mask[1]

  PORT LDQS = ddr_dqs_0_,   IO_IS = ddr_data_strobe[0]
  PORT UDQS = ddr_dqs_1_,   IO_IS = ddr_data_strobe[1]

  PORT DQ0  = ddr_dq_0_,    IO_IS = ddr_data[0]
  PORT DQ1  = ddr_dq_1_,    IO_IS = ddr_data[1]
  PORT DQ2  = ddr_dq_2_,    IO_IS = ddr_data[2]
  PORT DQ3  = ddr_dq_3_,    IO_IS = ddr_data[3]
  PORT DQ4  = ddr_dq_4_,    IO_IS = ddr_data[4]
  PORT DQ5  = ddr_dq_5_,    IO_IS = ddr_data[5]
  PORT DQ6  = ddr_dq_6_,    IO_IS = ddr_data[6]
  PORT DQ7  = ddr_dq_7_,    IO_IS = ddr_data[7]
  PORT DQ8  = ddr_dq_8_,    IO_IS = ddr_data[8]
  PORT DQ9  =  ddr_dq_9_,   IO_IS = ddr_data[9]
  PORT DQ10 = ddr_dq_10_,   IO_IS = ddr_data[10]
  PORT DQ11 = ddr_dq_11_,   IO_IS = ddr_data[11]
  PORT DQ12 = ddr_dq_12_,   IO_IS = ddr_data[12]
  PORT DQ13 = ddr_dq_13_,   IO_IS = ddr_data[13]
  PORT DQ14 = ddr_dq_14_,   IO_IS = ddr_data[14]
  PORT DQ15 = ddr_dq_15_,   IO_IS = ddr_data[15]

  PORT DDR_DQS_Div_O = ddr_dqs_div_io, IO_IS = DDR_DQS_Div_O
  PORT DDR_DQS_Div_I = ddr_dqs_div_io, IO_IS = DDR_DQS_Div_I
END

BEGIN FPGA
  ATTRIBUTE INSTANCE = fpga_0
  ATTRIBUTE FAMILY = spartan3a
  ATTRIBUTE  DEVICE =  XC3S1400a
  ATTRIBUTE PACKAGE =  FG484
  ATTRIBUTE SPEED_GRADE =  -4
  ATTRIBUTE JTAG_POSITION = 1
          
### CLOCK ###
  PORT CLK_10_P = CONN_CLK_P , UCF_NET_STRING=("LOC=D11", "IOSTANDARD = LVDS_33")       
  PORT CLK_10_N = CONN_CLK_N , UCF_NET_STRING=("LOC=E11", "IOSTANDARD = LVDS_33")       

### RESET ### This pin is the "south" pushbutton switch
   PORT RESET = CONN_FPGA.RESET, UCF_NET_STRING=("LOC=P16",  "IOSTANDARD = LVCMOS33", "PULLUP")
 
### UART ###
   PORT RXD_CP2102 = CONN_RXD_CP2102, UCF_NET_STRING=("LOC=AB3",  "IOSTANDARD = LVCMOS33")
   PORT TXD_CP2102 = CONN_TXD_CP2102, UCF_NET_STRING=("LOC=AB2", "IOSTANDARD = LVCMOS33")

### LED ###
   PORT LED7 = CONN_LED7, UCF_NET_STRING=("LOC=A15", "IOSTANDARD = LVCMOS33")
   PORT LED6 = CONN_LED6, UCF_NET_STRING=("LOC=A16", "IOSTANDARD = LVCMOS33")
   PORT LED5 = CONN_LED5, UCF_NET_STRING=("LOC=A17", "IOSTANDARD = LVCMOS33")
   PORT LED4 = CONN_LED4, UCF_NET_STRING=("LOC=C15", "IOSTANDARD = LVCMOS33")
   PORT LED3 = CONN_LED3, UCF_NET_STRING=("LOC=Y14", "IOSTANDARD = LVCMOS33")
   PORT LED2 = CONN_LED2, UCF_NET_STRING=("LOC=Y5",  "IOSTANDARD = LVCMOS33")
   PORT LED1 = CONN_LED1, UCF_NET_STRING=("LOC=W6",  "IOSTANDARD = LVCMOS33")  # This is the same as spi_cs_3
   PORT LED0 = CONN_LED0, UCF_NET_STRING=("LOC=AA4", "IOSTANDARD = LVCMOS33")  ### This pin is on Bank 0
   
### DIP_Switches ###
   PORT DIP1 = CONN_DIP1, UCF_NET_STRING=("LOC=E9  | PULLUP", "IOSTANDARD = LVCMOS33")
   PORT DIP2 = CONN_DIP2, UCF_NET_STRING=("LOC=E7  | PULLUP", "IOSTANDARD = LVCMOS33")
   PORT DIP3 = CONN_DIP3, UCF_NET_STRING=("LOC=C13 | PULLUP", "IOSTANDARD = LVCMOS33")
   PORT DIP4 = CONN_DIP4, UCF_NET_STRING=("LOC=D13 | PULLUP", "IOSTANDARD = LVCMOS33")

### BUTTONS ###
   PORT BUT1 = CONN_BUT1, UCF_NET_STRING=("LOC=R11 | PULLUP", "IOSTANDARD = LVCMOS33") # South
   PORT BUT2 = CONN_BUT2, UCF_NET_STRING=("LOC=T11 | PULLUP", "IOSTANDARD = LVCMOS33") # West
   PORT BUT3 = CONN_BUT3, UCF_NET_STRING=("LOC=R10 | PULLUP", "IOSTANDARD = LVCMOS33") # East
   PORT BUT4 = CONN_BUT4, UCF_NET_STRING=("LOC=B6  | PULLUP", "IOSTANDARD = LVCMOS33") # North
   PORT BUT5 = CONN_BUT5, UCF_NET_STRING=("LOC=B8  | PULLUP", "IOSTANDARD = LVCMOS33") # Center
   PORT BUT6 = CONN_BUT6, UCF_NET_STRING=("LOC=A8  | PULLUP", "IOSTANDARD = LVCMOS33") # Center

# M25P64 SPI Flash 64Mb
   PORT MISO = spi_MISO, UCF_NET_STRING=("LOC=AB20", "IOSTANDARD = LVCMOS33")
   PORT MOSI = spi_MOSI, UCF_NET_STRING=("LOC=AB14", "IOSTANDARD = LVCMOS33")
   PORT SCK = spi_SCK,   UCF_NET_STRING=("LOC=AA20", "IOSTANDARD = LVCMOS33")
   PORT SS0 = spi_cs,    UCF_NET_STRING=("LOC=Y4",   "IOSTANDARD = LVCMOS33")

# User Interface Board SPI Port
 PORT UI_MISO = fpga_0_SPI_UI_MISO, UCF_NET_STRING=("LOC=F7", "IOSTANDARD = LVCMOS33")
 PORT UI_MOSI = fpga_0_SPI_UI_MOSI, UCF_NET_STRING=("LOC=C14", "IOSTANDARD = LVCMOS33")
 PORT UI_SCK = fpga_0_SPI_UI_SCK,   UCF_NET_STRING=("LOC=E14", "IOSTANDARD = LVCMOS33")
 PORT UI_SS = fpga_0_SPI_UI_SS,     UCF_NET_STRING=("LOC=C16",   "IOSTANDARD = LVCMOS33")

# microSD Card 2GB
 PORT SD_MISO = fpga_0_SPI_SD_MISO, UCF_NET_STRING=("LOC=E13", "IOSTANDARD = LVCMOS33")
 PORT SD_MOSI = fpga_0_SPI_SD_MOSI, UCF_NET_STRING=("LOC=A14", "IOSTANDARD = LVCMOS33")
 PORT SD_SCK = fpga_0_SPI_SD_SCK,   UCF_NET_STRING=("LOC=F13", "IOSTANDARD = LVCMOS33")
 PORT SD_SS = fpga_0_SPI_SD_SS,     UCF_NET_STRING=("LOC=B15", "IOSTANDARD = LVCMOS33")

# AD7923 Octal 12-bit ADC
 PORT ADC_MISO = fpga_0_SPI_ADC_MISO, UCF_NET_STRING=("LOC=F22", "IOSTANDARD = LVCMOS33")
 PORT ADC_MOSI = fpga_0_SPI_ADC_MOSI, UCF_NET_STRING=("LOC=G19", "IOSTANDARD = LVCMOS33")
 PORT ADC_SCK = fpga_0_SPI_ADC_SCK,   UCF_NET_STRING=("LOC=H20", "IOSTANDARD = LVCMOS33")
 PORT ADC_SS = fpga_0_SPI_ADC_SS,     UCF_NET_STRING=("LOC=F21", "IOSTANDARD = LVCMOS33")

# AD5318 Octal 10-bit DAC
 PORT DAC_MOSI = fpga_0_SPI_DAC_MOSI, UCF_NET_STRING=("LOC=H21", "IOSTANDARD = LVCMOS33")
 PORT DAC_SCK = fpga_0_SPI_DAC_SCK,   UCF_NET_STRING=("LOC=K18", "IOSTANDARD = LVCMOS33")
 PORT DAC_SS = fpga_0_SPI_DAC_SS,     UCF_NET_STRING=("LOC=K17", "IOSTANDARD = LVCMOS33")

# AD9958 DDS IC
 PORT DDS_MISO = fpga_0_SPI_DDS_MISO, UCF_NET_STRING=("LOC=N21", "IOSTANDARD = LVCMOS33")
 PORT DDS_MOSI = fpga_0_SPI_DDS_MOSI, UCF_NET_STRING=("LOC=N20", "IOSTANDARD = LVCMOS33")
 PORT DDS_SCK = fpga_0_SPI_DDS_SCK,   UCF_NET_STRING=("LOC=N22", "IOSTANDARD = LVCMOS33")
 PORT DDS_SS = fpga_0_SPI_DDS_SS,     UCF_NET_STRING=("LOC=P18", "IOSTANDARD = LVCMOS33")

# AD9516 Clock Generator IC
 PORT CLKGEN_MISO = fpga_0_SPI_CLKGEN_MISO, UCF_NET_STRING=("LOC=W13", "IOSTANDARD = LVCMOS33")
 PORT CLKGEN_MOSI = fpga_0_SPI_CLKGEN_MOSI, UCF_NET_STRING=("LOC=Y10", "IOSTANDARD = LVCMOS33")
 PORT CLKGEN_SCK = fpga_0_SPI_CLKGEN_SCK,   UCF_NET_STRING=("LOC=Y7",  "IOSTANDARD = LVCMOS33")
 PORT CLKGEN_SS = fpga_0_SPI_CLKGEN_SS,     UCF_NET_STRING=("LOC=V10", "IOSTANDARD = LVCMOS33")

# ADF4108 PLL CH A IC
 PORT PLL_CHA_MISO = fpga_0_SPI_PLL_CHA_MISO, UCF_NET_STRING=("LOC=AB17", "IOSTANDARD = LVCMOS33")
 PORT PLL_CHA_MOSI = fpga_0_SPI_PLL_CHA_MOSI, UCF_NET_STRING=("LOC=Y15", "IOSTANDARD = LVCMOS33")
 PORT PLL_CHA_SCK = fpga_0_SPI_PLL_CHA_SCK,   UCF_NET_STRING=("LOC=W15", "IOSTANDARD = LVCMOS33")
 PORT PLL_CHA_SS = fpga_0_SPI_PLL_CHA_SS,     UCF_NET_STRING=("LOC=Y16", "IOSTANDARD = LVCMOS33")

# ADF4108 PLL CH B IC
# PORT MISO = fpga_0_SPI_PLL_CHB_MISO, UCF_NET_STRING=("LOC=F22", "IOSTANDARD = LVCMOS33")
 PORT PLL_CHB_MOSI = fpga_0_SPI_PLL_CHB_MOSI, UCF_NET_STRING=("LOC=V14", "IOSTANDARD = LVCMOS33")
 PORT PLL_CHB_SCK = fpga_0_SPI_PLL_CHB_SCK,   UCF_NET_STRING=("LOC=AB18", "IOSTANDARD = LVCMOS33")
 PORT PLL_CHB_SS = fpga_0_SPI_PLL_CHB_SS,     UCF_NET_STRING=("LOC=W16", "IOSTANDARD = LVCMOS33")

# ADF4108 PLL RF IC
 PORT PLL_RF_MISO = fpga_0_SPI_PLL_RF_MISO, UCF_NET_STRING=("LOC=V17", "IOSTANDARD = LVCMOS33")
 PORT PLL_RF_MOSI = fpga_0_SPI_PLL_RF_MOSI, UCF_NET_STRING=("LOC=AB19", "IOSTANDARD = LVCMOS33")
 PORT PLL_RF_SCK = fpga_0_SPI_PLL_RF_SCK,   UCF_NET_STRING=("LOC=V16", "IOSTANDARD = LVCMOS33")
 PORT PLL_RF_SS = fpga_0_SPI_PLL_RF_SS,     UCF_NET_STRING=("LOC=W18", "IOSTANDARD = LVCMOS33")

# UXN14M9P Clock Divider:
   PORT CLK_DIV_SEL8 = CONN_CLK_DIV_SEL8, UCF_NET_STRING=("LOC=E15", "IOSTANDARD = LVCMOS33")
   PORT CLK_DIV_SEL7 = CONN_CLK_DIV_SEL7, UCF_NET_STRING=("LOC=A20", "IOSTANDARD = LVCMOS33")
   PORT CLK_DIV_SEL6 = CONN_CLK_DIV_SEL6, UCF_NET_STRING=("LOC=B20", "IOSTANDARD = LVCMOS33")
   PORT CLK_DIV_SEL5 = CONN_CLK_DIV_SEL5, UCF_NET_STRING=("LOC=C19", "IOSTANDARD = LVCMOS33")
   PORT CLK_DIV_SEL4 = CONN_CLK_DIV_SEL4, UCF_NET_STRING=("LOC=D19", "IOSTANDARD = LVCMOS33")
   PORT CLK_DIV_SEL3 = CONN_CLK_DIV_SEL3, UCF_NET_STRING=("LOC=D18", "IOSTANDARD = LVCMOS33")
   PORT CLK_DIV_SEL2 = CONN_CLK_DIV_SEL2, UCF_NET_STRING=("LOC=E17", "IOSTANDARD = LVCMOS33")
   PORT CLK_DIV_SEL1 = CONN_CLK_DIV_SEL1, UCF_NET_STRING=("LOC=E12", "IOSTANDARD = LVCMOS33")
   PORT CLK_DIV_SEL0 = CONN_CLK_DIV_SEL0, UCF_NET_STRING=("LOC=C12", "IOSTANDARD = LVCMOS33")

# UXD20P Prescaler IC
   PORT CLK_DIV_PRE1 = CONN_CLK_DIV_PRE1, UCF_NET_STRING=("LOC=C18", "IOSTANDARD = LVCMOS33")
   PORT CLK_DIV_PRE0 = CONN_CLK_DIV_PRE0, UCF_NET_STRING=("LOC=F15", "IOSTANDARD = LVCMOS33")

# PE4309 Attenuator Channel A No. 1 IC
   PORT PE4309_CHA1_CTRL5 = CONN_PE4309_CHA1_CTRL5, UCF_NET_STRING=("LOC=G20", "IOSTANDARD = LVCMOS33")
   PORT PE4309_CHA1_CTRL4 = CONN_PE4309_CHA1_CTRL4, UCF_NET_STRING=("LOC=J18", "IOSTANDARD = LVCMOS33")
   PORT PE4309_CHA1_CTRL3 = CONN_PE4309_CHA1_CTRL3, UCF_NET_STRING=("LOC=H19", "IOSTANDARD = LVCMOS33")
   PORT PE4309_CHA1_CTRL2 = CONN_PE4309_CHA1_CTRL2, UCF_NET_STRING=("LOC=E20", "IOSTANDARD = LVCMOS33")
   PORT PE4309_CHA1_CTRL1 = CONN_PE4309_CHA1_CTRL1, UCF_NET_STRING=("LOC=F20", "IOSTANDARD = LVCMOS33")
   PORT PE4309_CHA1_CTRL0 = CONN_PE4309_CHA1_CTRL0, UCF_NET_STRING=("LOC=F19", "IOSTANDARD = LVCMOS33")

# PE4309 Attenuator Channel A No. 2 IC
   PORT PE4309_CHA2_CTRL5 = CONN_PE4309_CHA2_CTRL5, UCF_NET_STRING=("LOC=F18", "IOSTANDARD = LVCMOS33")
   PORT PE4309_CHA2_CTRL4 = CONN_PE4309_CHA2_CTRL4, UCF_NET_STRING=("LOC=E22", "IOSTANDARD = LVCMOS33")
   PORT PE4309_CHA2_CTRL3 = CONN_PE4309_CHA2_CTRL3, UCF_NET_STRING=("LOC=D22", "IOSTANDARD = LVCMOS33")
   PORT PE4309_CHA2_CTRL2 = CONN_PE4309_CHA2_CTRL2, UCF_NET_STRING=("LOC=D21", "IOSTANDARD = LVCMOS33")
   PORT PE4309_CHA2_CTRL1 = CONN_PE4309_CHA2_CTRL1, UCF_NET_STRING=("LOC=D20", "IOSTANDARD = LVCMOS33")
   PORT PE4309_CHA2_CTRL0 = CONN_PE4309_CHA2_CTRL0, UCF_NET_STRING=("LOC=C22", "IOSTANDARD = LVCMOS33")

# PE4309 Attenuator Channel B No. 1 IC
   PORT PE4309_CHB1_CTRL5 = CONN_PE4309_CHB1_CTRL5, UCF_NET_STRING=("LOC=Y18",  "IOSTANDARD = LVCMOS33")
   PORT PE4309_CHB1_CTRL4 = CONN_PE4309_CHB1_CTRL4, UCF_NET_STRING=("LOC=w17",  "IOSTANDARD = LVCMOS33")
   PORT PE4309_CHB1_CTRL3 = CONN_PE4309_CHB1_CTRL3, UCF_NET_STRING=("LOC=AB21", "IOSTANDARD = LVCMOS33")
   PORT PE4309_CHB1_CTRL2 = CONN_PE4309_CHB1_CTRL2, UCF_NET_STRING=("LOC=AA21", "IOSTANDARD = LVCMOS33")
   PORT PE4309_CHB1_CTRL1 = CONN_PE4309_CHB1_CTRL1, UCF_NET_STRING=("LOC=B2",   "IOSTANDARD = LVCMOS33")
   PORT PE4309_CHB1_CTRL0 = CONN_PE4309_CHB1_CTRL0, UCF_NET_STRING=("LOC=E6",   "IOSTANDARD = LVCMOS33")

# PE4309 Attenuator Channel B No. 2 IC
   PORT PE4309_CHB2_CTRL5 = CONN_PE4309_CHB2_CTRL5, UCF_NET_STRING=("LOC=B3",  "IOSTANDARD = LVCMOS33")
   PORT PE4309_CHB2_CTRL4 = CONN_PE4309_CHB2_CTRL4, UCF_NET_STRING=("LOC=C5",  "IOSTANDARD = LVCMOS33")
   PORT PE4309_CHB2_CTRL3 = CONN_PE4309_CHB2_CTRL3, UCF_NET_STRING=("LOC=C21", "IOSTANDARD = LVCMOS33")
   PORT PE4309_CHB2_CTRL2 = CONN_PE4309_CHB2_CTRL2, UCF_NET_STRING=("LOC=B22", "IOSTANDARD = LVCMOS33")
   PORT PE4309_CHB2_CTRL1 = CONN_PE4309_CHB2_CTRL1, UCF_NET_STRING=("LOC=B21", "IOSTANDARD = LVCMOS33")
   PORT PE4309_CHB2_CTRL0 = CONN_PE4309_CHB2_CTRL0, UCF_NET_STRING=("LOC=G18", "IOSTANDARD = LVCMOS33")

   
### DDR SDRAM 16Mx16

  PORT DDR_DQS_Div_IO = ddr_dqs_div_io, UCF_NET_STRING=("LOC=W3", IOSTANDARD = LVCMOS33), DIR = IO

  PORT DDR_CLK    = ddr_clk,     UCF_NET_STRING=("LOC=AA1", "IOSTANDARD = DIFF_SSTL2_I") 
#  PORT DDR_CLK_FB = ddr_clk_fb,  UCF_NET_STRING=("LOC=V4", "IOSTANDARD = LVCMOS33")
  PORT DDR_CLK_N  = ddr_clk_n,   UCF_NET_STRING=("LOC=AA2", "IOSTANDARD = DIFF_SSTL2_I")

  PORT DDR_A00   = ddr_addr_0_,  UCF_NET_STRING=("LOC=K5", "IOSTANDARD = SSTL2_I")
  PORT DDR_A01   = ddr_addr_1_,  UCF_NET_STRING=("LOC=K2", "IOSTANDARD = SSTL2_I")
  PORT DDR_A02   = ddr_addr_2_,  UCF_NET_STRING=("LOC=K3", "IOSTANDARD = SSTL2_I")
  PORT DDR_A03   = ddr_addr_3_,  UCF_NET_STRING=("LOC=L3", "IOSTANDARD = SSTL2_I")
  PORT DDR_A04   = ddr_addr_4_,  UCF_NET_STRING=("LOC=L5", "IOSTANDARD = SSTL2_I")
  PORT DDR_A05   = ddr_addr_5_,  UCF_NET_STRING=("LOC=L1", "IOSTANDARD = SSTL2_I")
  PORT DDR_A06   = ddr_addr_6_,  UCF_NET_STRING=("LOC=K1", "IOSTANDARD = SSTL2_I")
  PORT DDR_A07   = ddr_addr_7_,  UCF_NET_STRING=("LOC=M2", "IOSTANDARD = SSTL2_I")
  PORT DDR_A08   = ddr_addr_8_,  UCF_NET_STRING=("LOC=M1", "IOSTANDARD = SSTL2_I")
  PORT DDR_A09   = ddr_addr_9_,  UCF_NET_STRING=("LOC=M4", "IOSTANDARD = SSTL2_I")
  PORT DDR_A10   = ddr_addr_10_, UCF_NET_STRING=("LOC=M3", "IOSTANDARD = SSTL2_I")
  PORT DDR_A11   = ddr_addr_11_, UCF_NET_STRING=("LOC=Y2", "IOSTANDARD = SSTL2_I")
  PORT DDR_A12   = ddr_addr_12_, UCF_NET_STRING=("LOC=Y1", "IOSTANDARD = SSTL2_I")
  
  PORT DDR_BA0   = ddr_ba_0_,    UCF_NET_STRING=("LOC=H2", "IOSTANDARD = SSTL2_I")
  PORT DDR_BA1   = ddr_ba_1_,    UCF_NET_STRING=("LOC=K4", "IOSTANDARD = SSTL2_I")

  PORT DDR_CAS_N = ddr_cas_n,    UCF_NET_STRING=("LOC=G3", "IOSTANDARD = SSTL2_I")
  PORT DDR_CKE   = ddr_cke,      UCF_NET_STRING=("LOC=H1", "IOSTANDARD = SSTL2_I")
  PORT DDR_CS_N  = ddr_cs_n,     UCF_NET_STRING=("LOC=H4", "IOSTANDARD = SSTL2_I")
  PORT DDR_RAS_N = ddr_ras_n,    UCF_NET_STRING=("LOC=H3", "IOSTANDARD = SSTL2_I")
  PORT DDR_WE_N  = ddr_we_n,     UCF_NET_STRING=("LOC=G1", "IOSTANDARD = SSTL2_I")

  PORT DDR_LDQM  = ddr_dm_0_,    UCF_NET_STRING=("LOC=T4", "IOSTANDARD = SSTL2_I")
  PORT DDR_UDQM  = ddr_dm_1_,    UCF_NET_STRING=("LOC=R1", "IOSTANDARD = SSTL2_I")

  PORT DDR_LDQS  = ddr_dqs_0_,   UCF_NET_STRING=("LOC=U5", "IOSTANDARD = SSTL2_I")
  PORT DDR_UDQS  = ddr_dqs_1_,   UCF_NET_STRING=("LOC=N4", "IOSTANDARD = SSTL2_I", "PULLUP")

  PORT DDR_DQ00  = ddr_dq_0_,    UCF_NET_STRING=("LOC=W1", "IOSTANDARD = SSTL2_I", "PULLUP")
  PORT DDR_DQ01  = ddr_dq_1_,    UCF_NET_STRING=("LOC=W2", "IOSTANDARD = SSTL2_I", "PULLUP")
  PORT DDR_DQ02  = ddr_dq_2_,    UCF_NET_STRING=("LOC=U3", "IOSTANDARD = SSTL2_I", "PULLUP")
  PORT DDR_DQ03  = ddr_dq_3_,    UCF_NET_STRING=("LOC=U4", "IOSTANDARD = SSTL2_I", "PULLUP")
  PORT DDR_DQ04  = ddr_dq_4_,    UCF_NET_STRING=("LOC=V1", "IOSTANDARD = SSTL2_I", "PULLUP")
  PORT DDR_DQ05  = ddr_dq_5_,    UCF_NET_STRING=("LOC=V3", "IOSTANDARD = SSTL2_I", "PULLUP")
  PORT DDR_DQ06  = ddr_dq_6_,    UCF_NET_STRING=("LOC=U1", "IOSTANDARD = SSTL2_I", "PULLUP")
  PORT DDR_DQ07  = ddr_dq_7_,    UCF_NET_STRING=("LOC=U2", "IOSTANDARD = SSTL2_I", "PULLUP")
  PORT DDR_DQ08  = ddr_dq_8_,    UCF_NET_STRING=("LOC=R5", "IOSTANDARD = SSTL2_I", "PULLUP")
  PORT DDR_DQ09  = ddr_dq_9_,    UCF_NET_STRING=("LOC=R4", "IOSTANDARD = SSTL2_I", "PULLUP")
  PORT DDR_DQ10  = ddr_dq_10_,   UCF_NET_STRING=("LOC=R3", "IOSTANDARD = SSTL2_I", "PULLUP")
  PORT DDR_DQ11  = ddr_dq_11_,   UCF_NET_STRING=("LOC=R2", "IOSTANDARD = SSTL2_I", "PULLUP")
  PORT DDR_DQ12  = ddr_dq_12_,   UCF_NET_STRING=("LOC=P3", "IOSTANDARD = SSTL2_I", "PULLUP")
  PORT DDR_DQ13  = ddr_dq_13_,   UCF_NET_STRING=("LOC=P5", "IOSTANDARD = SSTL2_I", "PULLUP")
  PORT DDR_DQ14  = ddr_dq_14_,   UCF_NET_STRING=("LOC=P1", "IOSTANDARD = SSTL2_I", "PULLUP")
  PORT DDR_DQ15  = ddr_dq_15_,   UCF_NET_STRING=("LOC=P2", "IOSTANDARD = SSTL2_I", "PULLUP")
END