Parallel AES Encryption Engines for Many-Core Processor Arrays
Bevan M. Baas
VLSI Computation Laboratory
Department of Electrical and Computer Engineering
University of California, Davis
By exploring different granularities of data-level and task-level parallelism, we map 16 implementations of an
Advanced Encryption Standard (AES) cipher with both online and offline key expansion on a fine-grained many-core system.
The smallest design utilizes only 6 cores for offline key expansion and 8 cores for online key expansion, while the largest
requires 107 cores and 137 cores, respectively. In comparison with published AES cipher implementations on general purpose
processors, our design has 3.5-15.6 times higher throughput per unit of chip area and 8.2-18.1 times higher energy efficiency.
Moreover, the design shows 2.0 times higher throughput than the TI DSP C6201, and 3.3 times higher throughput per unit of
chip area and 2.9 times higher energy efficiency than the GeForce 8800 GTX.
Bin Liu and B. M. Baas,
"Parallel AES Encryption Engines for Many-Core Processor Arrays,"
to apprear on IEEE Transactions on Computers.
| ECE Dept.
| UC Davis
Last update: Dec. 20, 2011