A Reduced Routing Network Architecture for Partial Parallel LDPC Decoders

Houshmand Shirani-Mehr
Tinoosh Mohsenin
Bevan M. Baas
VLSI Computation Laboratory
Department of Electrical and Computer Engineering
University of California, Davis

Abstract:

A novel partial parallel decoding scheme based on the matrix structure of LDPC codes proposed in the IEEE 802.15.3c and IEEE 802.11ad standards is presented that significantly simplifies the routing network of the decoder, and the class of parity-check matrices for which the method can be used is defined. The proposed method results in an almost complete elimination of logic gates on the routing network, which yields improvements in area, speed and power, with an identical error correction performance to conventional partial-parallel decoders. A decoder for the (672,588) LDPC code adopted in IEEE 802.15.3c is implemented in a 65 nm CMOS technology including place &route with both proposed permutational decoder, and conventional partial-parallel architecture. The proposed permutational LDPC decoder operates at 235 MHz and delivers a throughput of 7.9 Gbps with 5 decoding iterations per block. The proposed permutational decoder has a throughput 30% higher and is approximately 24% smaller than the conventional partial-parallel decoder.

Paper

Presentation

Reference

Houshmand Shirani-Mehr, Tinoosh Mohsenin and Bevan M. Baas, "A Reduced Routing Network Architecture for Partial Parallel LDPC Decoders," IEEE Asilomar Conference on Signals, Systems and Computers (ACSSC) Nov. 2011.

BibTeX Entry

@INPROCEEDINGS{Hshirani:ACSSC2011,
   author={Houshmand Shirani-Mehr, Tinoosh Mohsenin and Bevan M. Baas},
   booktitle={IEEE Asilomar COnference on Signals, Systems and Computers ({ACSSC})}, 
   title={A Reduced Routing Network Architecture for Partial Parallel LDPC Decoders},
   year={2011},
   month={Nov.}
}

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Last update: Nov 17, 2011