A Low-Area Multi-Link Interconnect Architecture for GALS Chip Multiprocessors

Zhiyi Yu
Bevan M. Baas
VLSI Computation Laboratory
Department of Electrical and Computer Engineering
University of California, Davis

Abstract:

A new inter-processor communication architecture
for chip multiprocessors is proposed which has a low area cost,
flexible routing capability, and supports globally asynchronous
locally synchronous (GALS) clocking styles. To achieve a low area
cost, the proposed statically-configurable asymmetric architecture
assigns large buffer resources to only the nearest neighbor
interconnect and much smaller buffer resources for long distance
interconnect. To maintain flexible routing capability, each
neighboring processor pair has multiple connecting links. The
architecture supports long distance communication in GALS
systems by transferring the source clock with the data signals
along the entire path for write synchronization. Compared to a
traditional dynamically-configurable interconnect architecture
with symmetric buffer allocation and single-links between neighboring
processor pairs, this implementation has approximately
two times smaller communication circuitry area with a similar
routing capability. Area and speed estimates are obtained with the
physical design of seven chips in 0.18-um CMOS.

Paper

Reference

Zhiyi Yu; Baas, B.M.; , "A Low-Area Multi-Link Interconnect Architecture for GALS Chip Multiprocessors," Very Large Scale Integration (VLSI) Systems, IEEE Transactions on , vol.18, no.5, pp.750-762, May 2010

BibTeX Entry

@ARTICLE{Yu:TVLSI:2010,
    author={Zhiyi Yu and Baas, B.M.},
    journal={Very Large Scale Integration (VLSI) Systems, IEEE Transactions on}, 
    title={A Low-Area Multi-Link Interconnect Architecture for GALS Chip Multiprocessors},
    year={2010},
    month={may.},
    volume={18},
    number={5},
    pages={750-762},
    doi={10.1109/TVLSI.2009.2017912},
    ISSN={1063-8210}
}

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Last update: Sep. 07, 2010