A 167-Processor Computational Platform in 65 nm CMOS

Dean N. Truong
Wayne H. Cheng
Tinoosh Mohsenin
Zhiyi Yu
Anthony T. Jacobson
Gouri Landge
Michael J. Meeuwsen
Anh T. Tran
Zhibin Xiao
Eric W. Work
Jeremy W. Webb
Paul V. Mejia
Bevan M. Baas
VLSI Computation Laboratory
Department of Electrical and Computer Engineering
University of California, Davis

Abstract:

An 167-processor computational platform consists of an array of simple
programmable processors capable of per-processor dynamic supply voltage
and clock frequency scaling, three algorithm-specific processors, and 
three 16 KB shared memories; and is implemented in 65 nm CMOS.  All 
processors and shared memories are clocked by local fully independent, 
dynamically haltable, digitally-programmable oscillators and are 
interconnected by a configurable circuit-switched network which supports
long-distance communication.  Programmable processors occupy 0.17 mm2
and operate at a maximum clock frequency of 1.2 GHz at 1.3 V. At 1.2 V, they 
operate at 1.07 GHz and consume 47.5 mW when 100% active, resulting in an 
energy dissipation of 44 pJ per operation.  At 0.675 V, they operate at 
66 MHz and consume 608 µW when 100% active, resulting in a total 
energy dissipation of 9.2 pJ per ALU or MAC operation.

Paper

Reference

Dean N. Truong, Wayne H. Cheng, Tinoosh Mohsenin, Zhiyi Yu, Anthony T. Jacobson, Gouri Landge, Michael J. Meeuwsen, Anh T. Tran, Zhibin Xiao, Eric W. Work, Jeremy W. Webb, Paul V. Mejia, Bevan M. Baas, "A 167-Processor Computational Platform in 65 nm CMOS" IEEE Journal of Solid-State Circuits (JSSC), vol. 44, no. 4, pp. 1130-1144, April 2009.

BibTeX entry

@ARTICLE{Truong:JSSC:2009,
   author  = {Truong, D.N. and Cheng, W.H. and Mohsenin, T. and Zhiyi Yu and 
              Jacobson, A.T. and Landge, G. and Meeuwsen, M.J. and Watnik, C. 
              and Tran, A.T. and Zhibin Xiao and Work, E.W. and Webb, J.W. and 
              Mejia, P.V. and Baas, B.M.},
   journal = {Solid-State Circuits, IEEE Journal of}, 
   title   = {A 167-Processor Computational Platform in 65 nm {CMOS}},
   year    = 2009},
   month   = apr,
   volume  = 44},
   number  = 4},
   pages   = 1130-1144},
   doi     = 10.1109/JSSC.2009.2013772},
   ISSN    = 0018-9200}
}

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Last update: Sep. 27, 2010