Performance and Power Analysis of Globally Asynchronous Locally Synchronous Multi-Processor Systems

Zhiyi Yu
Bevan M. Baas
VLSI Computation Laboratory
Department of Electrical and Computer Engineering
University of California, Davis

Abstract:

This paper investigates the performance and power dissipation of Globally Asynchronous Locally Synchronous (GALS) Multi-processor Systems. We show that communication loops are a source of significant throughput degradation in communications links and that there is no degradation whatsoever under certain conditions for one-way links, and that it is possible to design GALS multi-processors without this performance penalty. Independent clock domains and unbalanced computation in the GALS multi-processor allow scaling of the clock frequency and supply voltage to achieve high energy efficiency. The synchronization overhead between independent clock domains results in a less than 1% performance reduction compared to a globally synchronous system over a number of DSP and numerical applications. Clock and voltage scaling can achieve an approximately 40% power savings with no reduction of performance. These results compare favorably with the 25% power savings and more than 10% performance reduction reported for GALS uniprocessors.

Paper

Presentation Slides

Reference

Zhiyi Yu, Bevan M. Baas. "Performance and Power Analysis of Globally Asynchronous Locally Synchronous Multi-processor Systems" In Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI) , March 2006, pp.378-384.

BibTeX entry

@inproceedings{UCDVCL:2006:ISVLSI,
   author    = {Zhiyi Yu and Bevan M. Baas},
   title     = {Performance and Power Analysis of Globally Asynchronous Locally
     Synchronous Multi-processor Systems},
   booktitle = {IEEE Computer Society Annual Symposium on VLSI (ISVLSI) },
   month     = March,
   year      = 2006
   }

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Last update: March 10, 2006