[VLSI Computation Lab]

Asynchronous Array of simple Processors (AsAP) Version 1 Development Board

Welcome to the AsAP Version 1 development board web page. This page contains information on the AsAP Version 1 development board.

AsAP web pages:

Schematics and Layout:

Board Stack-Up:

        TOP    - ROUTING - TOP
        GND    - PLANE   - GND
        VIO    - PLANE   - PWR
        INNER1 - ROUTING - IN1
        VOSC   - PLANE   - IN2
        GND3   - PLANE   - IN3
        INNER4 - ROUTING - IN4
        VCORE  - PLANE   - IN5
        GND2   - PLANE   - IN6

Board Turn-on Results:

Part Data Sheets:

Configuration FPGA:

ECE Dept. | UC Davis | AsAP Demo Board Comparisons | AsAP Development Board Ideas

Last update: September 11, 2006

Keywords: electrical engineering, computer engineering, university, academic, department, group, lab, laboratory, research development, chip, VLSI, CMOS, circuit, low power, energy efficient, FFT, DCT, viterbi, FIR, IIR, compression, communication, coding, convolution, correlation, encryption, image, video, JPEG, multimedia, wireless, OFDM, radar, sonor, medical imaging, MRI, magnetic resonance imaging, biological imaging, 802.11a, 802.11g, wireless LAN, transmitter, receiver.