66 U.C. Berkeley Low-Power Cell Library

(from Tom Burd <burd@eecs.berkeley.edu>)

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		      U.C. Berkeley Low-Power Cell Library
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  FOR CONDITIONS OF USE, PLEASE READ THE ACCOMPANYING COPYRIGHT FILE
				Overview:
				--------
This library has been used in the development of over a dozen chips here at U.C. Berkeley as of Dec. 1994, so it has been through several rounds of beta testing already.

Since the library is naturally partioned by the type of cell, I have set up separate distributions for each partition:

1. TimLagerlp 	       Array tiled cells. (e.g. sram, fifo, etc.)
2. dpplp      	       Bitsliced cells for datapath construction.
3. stdcell2_3lp	       Standard Cell Library.
4. pads1_0clp	       1.0um pads.
5. pads1_2clp	       1.2um pads.
PLEASE SEND BUG-REPORTS TO burd@eecs.berkeley.edu AND PREFIX THE SUBJECT LINE WITH "LPLIB BUG:" FOR EASIER ACCOUNTING.

PLEASE DO NOT DIRECT INQUIRES REGARDING HOW TO USE LAGERIV, POWERVIEW(TM), OR FRAMEMAKER(TM) TO MYSELF, BUT RATHER TO AN APPROPRIATE NEWS GROUP DISCUSSION.

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			      Installation:
			      -------------
1. Untar the desired partitions in an installation directory (denoted
   as LPLIB)
2. To use with LagerIV, I have also included a "lager" file here to
   be used, that will function properly if the LPLIB environment
   variable is set.
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			      Documentation:
			      -------------
2. Spice Files: I have included here the 1.2um and 1.0um spice files used for the timing. All delays are measured 50%-50%. The BSIM models for used and simulated with HSPICE (Trademark Meta Software).

3. You can also refer to my thesis for further overview of the design choices made, and an overview of the Library:

	<URL:http://infopad.eecs.berkeley.edu/~burd/gpp/gpp.html#masters>
	<URL:ftp://infopad.eecs.berkeley.edu/pub/burd/masters.ps>

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