62 LOG/iC, a logic synthesis package for PLDs

(from Ralph Remme <RR@ns.isdata.de>)

LOG/iC EVAL
- - ISDATA GmbH Karlsruhe, Germany / ISDATA Inc. Oakland CA
- - FSM and logic synthesis for programmable logic devices
- - Several output formats: JEDEC, POF, HEX, EDIF, XNF, Open-PLA,
    PALASM, ...
- - PLD data base as an electronic reference
- - PC Windows
- - free version of LOG/iC PLUS for educational and research use only
- - anonymous ftp: ftp://gate.fzi.de/pub/ISDATA (141.21.4.3)
- - email: isdata@isdata.de
ISDATA GmbH			ISDATA Inc.
Daimlerstrasse 51		P.O. Box 19278
D-76185 KARLSRUHE		Oakland, CA 94619
GERMANY				U.S.A.
Phone:(+49) 721 75 10 87	Phone: (++1) 510 5318553
FAX:   (+49) 721 75 26 34	Fax:   (++1) 510 5318417
Mr. Peter Bauer			Mr. Paul Hoy
An evaluation copy of LOG/iC2 is available:

LOG/iC2 EVAL
- ISDATA, Germany
- Logic synthesis and simulation for PLDs 16V8, 20V8 and 22V10 from all
  manufacturers
- Input: Hierarchical entry supported by the graphical hierarchy
  editor, high level description language, 74xx library,
  macrogenerator
- Output: Programming file (JEDEC)
- includes the PLD data base, an electronic reference manual
- Functional simulator
- PC version for Win 3.1 and Win 95
- CD can be ordered free of charge at ISDATA via email: isdata@isdata.de
The full version of LOG/iC2 supports CPLDs from nearly all vendors,
FPGAs from Xilinx and Actel, and all Simple PLDs.
It offers timing simulation and as an option VHDL entry.

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