53 SLS, a switch-level simulator

(from comp.lsi.cad)

DELFT UNIVERSITY OFFERS UNIQUE SWITCH-LEVEL SIMULATOR

SLS is a switch-level simulator that can be used to simulate the logic and timing behavior of large digital circuits that are described at the (mixed) MOS transistor, gate and functional level. It has fast and accurate algorithms to predict the timing behavior of MOS circuits containing > 100,000 transistors. MOS transistor-level circuit descriptions are easily mixed with gate-level and functional-level circuit descriptions, where the behavior of the latter are described in the C programming language. There is an X-window based user-interface to graphically edit the input signals and to inspect the simulation output signals. The same interface is used to alternatively simulate the circuit with the well-known circuit simulator SPICE. SLS has already been used by many people at many different sites, and numerous chips have been designed with it. SLS is now made available world-wide to serve as a useful design and verification tool to the international design community. Apart from being used as a stand-alone tool, SLS can also be used as a part of the popular design system for Sea-Of-Gates circuits OCEAN, or it can be connected to the advanced Nelsis CAD framework.

The SLS simulator has three different simulation levels:

1. Purely logic simulation based on abstract transistor strengths: This level more or less behaves similar to the original switch-level model as proposed by R.E. Bryant. It computes logic states by only considering node states and transistor types. 2. Logic simulation based on exact transistor dimensions and node capacitances: This level uses resistance division and capacitance division algorithms to compute logic states. It finds correct logic states in much more situations than conventional switch-level simulators, e.g. when a resistance division occurs between a saturated transistor and a non-saturated transistor. 3. Logic and timing simulation based on transistor and node parameters: RC time constant evaluations are used to approximate real voltages by PIECEWISE-LINEAR VOLTAGE WAVEFORMS. This not only provides delay times for the circuit, but is also delivers an accurate representation for transient effects like spikes and races.

Availability:

SLS is written in C and runs under UNIX and X-windows. It runs, among other things, on Sun SPARC stations, HP 9000 series 700/800 machines, and PCs running Linux. The program is available for free under the terms of the GNU General Public License. It can be retrieved via anonymous ftp from ftp://dutentb.et.tudelft.nl/pub/sls .

It is also possible to obtain SLS as a part of the OCEAN system for the design of Sea-Of-Gates circuits. This system can be obtained from on ftp://donau.et.tudelft.nl/pub/ocean . The OCEAN system among other things contains a layout-to-circuit extractor that can extract large layouts and that stores the result directly in the database that is read by SLS. Furthermore, SLS is available as a tool in the Nelsis CAD framework from the directory pub/nelsis on dutente.et.tudelft.nl. The latest version of SLS can always be found on dutentb.et.tudelft.nl .

For questions, remarks and bug reports, contact

  Arjan van Genderen
  Delft University of Technology
  Department of Electrical Engineering
  Mekelweg 4                          phone: 31-15-786258
  2628 CD  Delft                      fax: 31-15-623271
  The Netherlands                     email: arjan@dutentb.et.tudelft.nl

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