42 WireC graphical/procedural system for schematic information

(From Larry McMurchie <larry@cs.washington.edu>)

WireC is a graphical specification language that combines schematics with procedural constructs for describing complex microelectronic systems. WireC allows the designer to choose the appropriate representation, either graphical or procedural, at a fine-grain level depending on the characteristics of the circuit being designed. Drawing traditional schematic symbols and their interconnections provides fast intuitive interaction with a circuit design while procedural constructs give the power and flexibility to describe circuit structures algorithmically and allow single descriptions to represent whole families of devices.

The procedural capability of WireC allows other CAD tools to be incorporated into the design system. For example, we have defined an interface to the SIS logic synthesis system wherein the designer can represent part of the system behaviorally. WireC invokes logic synthesis on these components to produce a structural description that can be incorporated into the rest of the design.

Libraries of devices defining a particular netlist output format may be defined by the user. The libraries currently distributed with WireC include a default CMOS gate library whose output is the SIM format. This format can be simulated with COSMOS or IRSIM and compared against a circuit extracted from layout. This library also includes devices that allow a behavioral description to be synthesized and mapped using MIS or SIS and incorporated into a larger circuit.

Another library is the xnf library for designing systems with Xilinx FPGAs. Written by Jackson Kong, Martine Schlag and Pak Chan of UCSC, this library contains devices specific to the 2000 and 3000 series Xilinx LCA's. In addition to drawing the devices explicitly, one can represent parts of a circuit with equations and have these synthesized automatically.

Currently in progress is a library of CMOS gates for Cascade Design Automation's ChipCrafter product. WireC provides a mixed schematic/procedural design frontend for ChipCrafter, which uses module generation, timing analysis and place and route software to create a physical layout from the WireC design specification.

WireC was written by Larry McMurchie, Carl Ebeling, Zhanbing Wu and Ed Tellman. We are interested in any libraries you may develop and will provide a limited degree of support.

WireC requires an X-Windows compatible environment and a C++ compiler such as Gnu G++ and AT&T CC. WireC is available via ftp on the Internet. For details send mail to

larry@cs.washington.edu ebeling@cs.washington.edu

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