16 What synthesis systems are there?

Thanks to Simon Leung <sleung@sun1.atitech.ca>, Michel Berkelaar <michel@ele.tue.nl>, Noritake Yonezawa <yonezawa@cs.uiuc.edu>, Donald A Lobo <lobo@guardian.cs.psu.edu>, Greg Ward <gregw@bnr.ca>, Peter Duzy, Robert Walker <walkerb@turing.cs.rpi.edu>, Heinrich Kraemer <kraemer@fzi.de>, Luciano Lavagno <luciano@ic.eecs.berkeley.edu>

L
ADPS
- Case Western Reserve University, USA
- scheduling and data path allocation
- Papachristou, C.A. et al.: "A Linear Program Driven Scheduling and
  Allocation Method Followed by an Interconnect Optimization Algorithm",
  Proc. of the 27th DAC, pp. 77-83, June 1990.
ALPS/LYRA/ARYL
- Tsing Hua University
- scheduling and data path allocation
- Lee, J-H: et al.: "A New Integer Linear Programming Formulation of
  the Scheduling Problem in Data Path Synthesis", Proc. of ICCAD89, pp.
  20-23, November 1989.
BDSYN
- University of California, Berkeley, USA
- FSM synthesis from DECSIM language for multilevel combination-logic
  realization
- Brayton, R.: "Multiple-level Logic Optimization System",  Proc. of IEEE
  ICCAD, Santa Clara, Nov. 1986
BECOME
- AT & T Bell Labs, USA
- FSM synthesis from C-like language for PLA, PLD and standard cell realization
- Wei, R-S.: "BECOME: Behavior Level Circuit Synthesis Based on Structure
  Mapping", Proc. of 25th ACM/IEEE Design Automation Conference, pp. 409-414,
  IEEE, 1988
BOLD
- logic optimization
- Bartlett, K. "Synthesis and Optimization of Multilevel Logic Under Timing
  Constraints", IEEE Transactions on Computer-Aided Design, Vol 5, No 10,
  October 1986
BRIDGE
- AT & T Bell Labs, USA
- High-level synthesis FDL2-language descriptions
- Tseng: "Bridge: A Versatile Behavioral Synthesis System", Proc. of 25th
  ACM/IEEE Design Automation Conference, pp. 415-420, IEEE, 1988
CADDY
- Karlsruhe University, Germany
- behavioral synthesis using VHDL as the input/output language, based on
  data-flow analysis; automated component selection (allocation), scheduling,
  and assignment. Different architechture styles are supported, such as
  multiplexers vs busses and two-phase vs single phase clocks.
- Camposano, R.: "Synthesing Circuits From Behavioral Descriptions", IEEE
  Transactions on Computer-Aided Design, Vol. 8, No. 2, February 1989
  Rosenstiel, W., Kraemer, H.: "Scheduling and Assignment in High-Level
  Synthesis", in 'High-Level VLSI-Synthesis' R. Camposano, W. Wolf Ed.
  Kluwer, 1991
  Gutberlet P., Mueller J., Kraemer H., Rosenstiel W.: "Automatic Module
  Allocation in High-level Synthesis", Proc. of 1st EURO-DAC, 1992
CALLAS
- Siemens, Germany
- highlevel, algortihmic and logic synthesis (contains CADDY, see
  above)
- Koster, M. et al.: "ASIC Design Using the High-Level Synthesis
  System CALLAS: A Case Study", Proc. IEEE International Conference on
  Computer Design (ICCD '90), pp. 141-146, Cambridge, Massachusetts,
  Sept. 17-19, 1990
CAMAD
- Linkoping University, Sweden
- scheduling, data path allocation and iteration from a Pascal subset
- Peng, Z.: "CAMAD: A Unified Data Path/ Control Synthesis
  Environment", Proc. of the IFIP Working Conference on Design
  Methodologies for VLSI and Computer Architecture, pp. 53-67, Sept.
  1988.
CARLOS
- Karlsruhe University, Germany
- multilevel logic optimization for CMOS realizations
- Mathony, H-J.: "CARLOS: An Automated Multilevel Logic Design System for
  CMOS Semi-Custom Integrated Circuits", IEEE Transactions on Computer-Aided
  Design, Vol 7, No 3, pp. 346-355, March 1988
CATHEDRAL
- Univ. of Leuve, Phillips and Siemens, Belgium
- synthesis of DSP-circuits from algorithm descriptions
- De Man, H.: "Architecture-Driven Synthesis Techiques for VLSI Implementation
  of DSP Algorithms", Proceedings of the IEEE, Vol. 78, NO. 2, pp. 319,
  February 1990
CATREE
- Univ. of Waterloo, Canada
- scheduling and data path allocation
- Gebotys, C.H.: "VLSI Design Synthesis with Testability", Proc. of
  the 25th DAC, pp. 16-21, June 1988
CHARM
- AT & T Bell Labs., USA
- data-path synthesis
- Woo, N-S.: "A Global, Dynamic Register Allocation and Binding for a
  Data Path Synthesis System", Proc. of the 27th DAC, pp. 505-510, June 1990.
CMU-DA (2)
- Carnagie-Mellon University, USA
- behavioral synthesis from ISPS
- Thomas, D.: "Linking the Behavioral and Structural Domains of Representation
  for Digital System Design", IEEE Transactions on Computer-Aided Design, pp.
  103-110, Vol. 6, No. 1, January 1987
CONES
- AT & T Bell Labs, USA
- FSM synthesis, produces 2-level logic realizations (truth-table)
- Stroud, C.E.: "CONES: A System for Automated Synthesis of VLSI and
  programmable logic from behavioral models", Proc. of IEEE ICCAD, Santa Clara,
  Nov. 1986.
DAGAR
- University of Texas, Austin, USA.
- scheduling and data-path allocation
- Raj. V.K.: "DAGAR: An Automatic Pipelined Microarchitecture
  Synthesis System", Proc. of ICCD '89, pp. 428-431, October 1989.
DELHI
- IIT
- design iteration, scheduling and data path allocation
- Balakrishnan, M. et al.: "Integrated Scheduling and Binding: A
  Synthesis Approach for Design Space Exploration", Proc. of the 26th
  DAC, pp. 68-74, June 1989
DESIGN AUTOMATION ASSISTANT (DAA)
- AT & T Bell Labs, USA
- expert system for data path synthesis
- Kowalski, T.J. "The VLSI Desig Automation Assistant: An Architecture
  Compiler", Silicon Compilation, pp. 122-152, Addison-Wesley, 1988
ELF
- Carleton University, Canada
- scheduling and data path allocation
- Girczyc, E.F. et al.: "Applicability of a Subset of Ada as an
  Algorithmic Hardware Description Language for Graph-Based Hardware
  Compilation", IEEE Trans. on CAD, pp. 134-142, April 1985.
EUCLID
- Eindhoven University of Technology, Netherlands
- logic synthesis
- Berkelaar, Michel R.C.M. and Theeuwen, J.F.M., "Real Area-Powe-Delay
  Trade-off in the EUCLID Logic Synthesis System" , proceedings of the Custom
  Integrated Circuits Conference 1990, Boston MA USA, pp 14.3.1 ff
EXLOG
- NEC Corporation, Japan
- expert system, synthesizes gate level circuits from FDL descriptions
- M. Watanabe, et al.,: "EXLOG: An Expert System for Logic Synthesis in
  Full-Custom VLSI Design", Proc. of 2nd Int. Conf. Application of Artificial
  Intelligence, August 1987.
FACE/PISYN
- General Electric, USA
- FACE: high-level synthesis tools and a tool framework, PISYN:
  synthesis of pipelined architecture DSP systems (mostly)
- Smith, W.D. et al.: "FACE Core Environment: The Model and it's
  Application in CAE/CAD Tool Development", Proc. of the 26th DAC, pp.
  466-471, June 1989.
FLAMEL
- Stanford University, USA
- data path and control-logic synthesis from Pascal description
- Trickey, H. "Flamel: A High-Level Hardware Compiler", IEEE Transactions
  on Computer-Aided Design, Vol 6, No 2, March 1987.
HAL
- Carleton University, Canada
- data path synthesis
- Paulin, P.: "Force-Directed Scheduling for the Behavioral Synthesis of
  ASIC's", IEEE Transaction on Computer-Aided Design, pp. 661,
  Vol. 8, No. 6, June 1989.
HARP
- NTT, Japan
- scheduling and data path-allocation from FORTRAN
- Tanaka, T. et al.: "HARP: Fortran to Silicon", IEEE Trans. on CAD,
  pp. 649-660, June 1989.
HYPER
- UCB, USA
- synthesis for realtime applications (scheduling, allocation, module
  binding, controller design)
- Chu, C-M. et al.: "HYPER: An Interactive Synthesis Environment for
  Real Time Applications", Proc. of ICCD '89, pp. 432-435, October 1989
IMBSL/RLEXT
- Univ. of Illinois, USA
- data-path allocation, RTL-level design
- Knapp D.W.: "Manual Rescheduling and Incremental Repair of Register
  Level Data Paths", Proc. of ICCAD '89, pp.58-61, November 1989.
LSS (Logic Synthesis System)
- IBM, USA
- logic synthesis and optimization from many RTL-languages
- Darringer, J. et al. "LSS: A System for Production Logic Synthesis",
  IBM Journal of Research and Developement, vol. 28, No. 5, pp. 272-280,
  Sept 1984.
MAHA
- University of Southern California, USA
- data path synthesis
- Parker, A.C. "MAHA: A Program for Data Path Synthesis", Proc. 23rd ACM/IEEE
  Design Automation Conference, pp. 252-258, IEEE 1986.
MIMOLA
- University of Dortmund, Germany
- scheduling, data-path allocation and controller design
- Marwedel, P. "Matching System And Component Behavior in MIMOLA
  Synthesis Tools", Proc. of EDAC '90, pp. 146-156, March 1990.
OLYMPUS/HERCULES
- Stanford University, USA
- behavioral synthesis from C-language (HERCULES), logic and physical
  synthesis
- De Micheli, G.: "HERCULES - A System for High-Level Synthesis", Proceedings
  of the 25th ACM/IEEE Design Automation Conference, pp. 483-488, IEEE 1988
SEHWA
- University of Southern California, USA
- pipeline-realizations from behavioral descriptions
- Park, N. "SEWHA: A Program for Synthesis of Pipelines", Proc. 23rd ACM/IEEE
  Design Automation Conference, pp. 454-460, IEEE 1986.
SIEMENS' SYNTHESIS SYSTEM
- Siemens, Germany
- partitioning, data path allocation and scheduling
- Scheichenzuber, J. et al.: "Global Hardware Synthesis from
  Behavioral Dataflow Descriptions", Proc. of the 27th DAC, pp. 456-461,
  June 1990.
SIS (formerly MIS (II/MV))
- University of California, Berkeley, USA
- synthesis and verification system for sequential logic
- E. M. Sentovich, K. J. Singh, L. Lavagno, C. Moon, R. Murgai,
  A. Saldanha, H. Savoj, P. R. Stephan, R. K. Brayton,
  A. Sangiovanni-Vincentelli: "SIS: A System for Sequential Circuit
  Synthesis", Tech report UCB/ERL M92/41, University of California,
  Berkeley, CA, May 1992
SOCRATES
- General Electric, University of Colorado, USA
- expert system
- logic optimization and mapping for different technologies
- de Geus, A.J., "The Socrates Logic Synthesis and Optimization System",
  Design Systems for VLSI Circuits, pp. 473-498, Martinus Nijhoff Publishers,
  1987.
SPAID
- Universty of Waterloo, Canada
- DSP-synthesis for silicon compiler realizations
- Haroun, B.: "Architectural Synthesis for DSP Silicon Compilers", IEEE
  Transactions on Computer-Aided Design, pp. 431-447, Vol. 8, No 4, April 1989.
SYNFUL
- Bell-Northern Research, Canada
- RTL and FSM synthesis for a production environment
- G. Ward, "Logic Synthesis at BNR: A SYNFUL Story", Proceedings
  Canadian Conference on Very Large Scale Integration, October 1990.
SYSTEM ARCHITECT'S WORKBENCH
- Carnagie-Mellon University, USA
- behavioral synthesis
- Thomas, D. "The System Architect's Workbench", Proceedings of the 25th
  ACM/IEEE Design Automation Conference, pp. 337-343, IEEE 1988
UCB'S SYNTHESIS SYSTEM
- UCB, USA
- transformations, scheduling and data path allocation
- Devadas, S.: "Algorithms for Hardware Allocation in Data Path
  Synthesis", IEEE Trans. on CAD, pp. 768-781, July 89
V COMPILER
- IBM, USA
- scheduling and data path allocation from V-language
- Berstis, V: "The V Compiler: Automatic Hardware Design", IEEE Design
  and Test, pp. 8-17, April 1989.
VSS
- Univ. of California at Irvine, USA
- transformations, scheduling and data path allocation from VHDL to
  MILO
- Lis, J. et al.: "Synthesis from VHDL", Proc. ICCD'88, pp. 378-381,
  October 1988.
YORKTOWN SILICON COMPILER
- IBM T.J.Watson Research Centre, USA
- data path synthesis, logic synthesis etc.
- Brayton, R.K., et al. "The Yorktown Silicon Compiler", Silicon Compilation,
  pp. 204-311, Addison-Wesley, 1988

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