Cites

Recent SSCRL Publications 1989-…


Note: This list contains only papers listed in the INSPEC database and so may be incomplete and/or out of date.


  1. Blecker EB, McDonald TM, Erdogan OE, Hurst PJ, Lewis SH. Digital background calibration of an algorithmic analog-to-digital converter using a simplified queue. [Journal Paper] IEEE Journal of Solid-State Circuits, vol.38, no.6, June 2003, pp.1059-62. Publisher: IEEE, USA.
  2. Keane JP, Le MQ, Hurst PJ. Analog timing recovery for a noise-predictive decision-feedback equalizer. [Journal Paper] IEEE Journal of Solid-State Circuits, vol.38, no.2, Feb. 2003, pp.338-42. Publisher: IEEE, USA.
  3. Jamal SM, Daihong Fu, Chang NC-J, Hurst PJ, Lewis SH. A 10-b 120-Msample/s time-interleaved analog-to-digital converter with digital background calibration. [Journal Paper] IEEE Journal of Solid-State Circuits, vol.37, no.12, Dec. 2002, pp.1618-27. Publisher: IEEE, USA.
  4. Keane JP, Le MQ, Hurst PJ. Analog timing recovery for a noise-predictive DFE. [Conference Paper] ESSCIRC 2002. Proceedings of the 28th European Solid-State Circuit Conference. Univ. Bologna. 2002, pp.243-6. Bologna, Italy.
  5. Jingyu Huang, Spencer RR. Filter design for 1000BASE-T analog front ends. [Conference Paper] 2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353). IEEE. Part vol.2, 2002, pp.II-572-5 vol.2. Piscataway, NJ, USA.
  6. Guo YB, Current KW. Voltage comparator circuits for multiple-valued CMOS logic. [Conference Paper] Proceedings 32nd IEEE International Symposium on Multiple- Valued Logic. IEEE Comput. Soc. 2002, pp.67-73. Los Alamitos, CA, USA.
  7. Jamal SM, Daihong Fu, Hurst PJ, Lewis SH. A 10b 120MSample/s time-interleaved analog-to-digital converter with digital background calibration. [Conference Paper] 2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315). IEEE. Part vol.1, 2002, pp.172-457 vol.1. Piscataway, NJ, USA.
  8. Jingyu Huang, Spencer RR. Simulated performance of 1000BASE-T receiver with different analog front end designs. [Conference Paper] Conference Record of Thirty-Fifth Asilomar Conference on Signals, Systems and Computers (Cat.No.01CH37256). IEEE. Part vol.1, 2001, pp.617-20 vol.1. Piscataway, NJ, USA.
  9. Le MQ, Hurst PJ, Keane JP. An adaptive analog noise-predictive decision-feedback equalizer. [Journal Paper] IEEE Journal of Solid-State Circuits, vol.37, no.2, Feb. 2002, pp.105-13. Publisher: IEEE, USA.
  10. Jun Ming, Lewis SH. An 8-bit 80-Msample/s pipelined analog-to-digital converter with background calibration. [Journal Paper] IEEE Journal of Solid-State Circuits, vol.36, no.10, Oct. 2001, pp.1489-97. Publisher: IEEE, USA.
  11. Tong A, Hurst PJ. A mixed-signal tuning approach for continuous-time LPFs. [Conference Paper] ISCAS 2001. The 2001 IEEE International Symposium on Circuits and Systems (Cat. No.01CH37196). IEEE. Part vol. 1, 2001, pp.192-5 vol. 1. Piscataway, NJ, USA.
  12. Current KW. Quaternary static latch circuit. [Journal Paper] International Journal of Electronics, vol.88, no.4, April 2001, pp.449-52. Publisher: Taylor & Francis, UK.
  13. Current KW, Wei-Shang Chu. Demonstration of an analog IC function maintenance strategy, including direct calibration, built-in self-test, and commutation of redundant functional blocks. [Journal Paper] Analog Integrated Circuits & Signal Processing, vol.26, no.2, Feb. 2001, pp.129-40. Publisher: Kluwer Academic Publishers, Netherlands.
  14. Current KW. Ternary static latch circuit. [Journal Paper] International Journal of Electronics, vol.88, no.1, Jan. 2001, pp.53-8. Publisher: Taylor & Francis, UK.
  15. Le MQ, Hurst PJ, Keane JP. An adaptive analog noise-predictive decision-feedback equalizer. [Conference Paper] 2000 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.00CH37103). IEEE. 2000, pp.216-17. Piscataway, NJ, USA.
  16. Xiaodong Wang, Spencer RR. A two-path tree search algorithm for use with DFE. [Journal Paper] IEEE Transactions on Communications, vol.48, no.6, June 2000, pp.913-16. Publisher: IEEE, USA.
  17. Zeng RW, Hurst PJ. A comparison of noise-shaping clock generators for switched-capacitor filters. [Journal Paper] IEEE Transactions on Circuits & Systems II-Analog & Digital Signal Processing, vol.47, no.6, June 2000, pp.544-7. Publisher: IEEE, USA.
  18. Jun Ming, Lewis SH. An 8b 80MSample/s pipelined ADC with background calibration. [Conference Paper] 2000 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.00CH37056). IEEE. 2000, pp.42-3, 446. Piscataway, NJ, USA.
  19. Xiaodong Wang, Spencer RR. A CMOS two-path tree search detector. [Journal Paper] IEEE Journal of Solid-State Circuits, vol.35, no.6, June 2000, pp.816-25. Publisher: IEEE, USA.
  20. Current KW. Design of a quaternary latch circuit using a binary CMOS RS latch. [Conference Paper] Proceedings 30th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2000). IEEE Comput. Soc. 2000, pp.377-81. Los Alamitos, CA, USA.
  21. Le MQ, Hurst PJ, Wang X. An adaptive noise-predictive decision-feedback equalizer for the magnetic recording channel. [Conference Paper] 1999 IEEE Pacific Rim Conference on Communications, Computers and Signal Processing (PACRIM 1999). Conference Proceedings (Cat. No.99CH36368). IEEE. 1999, pp.560-3. Piscataway, NJ, USA.
  22. Roo P, Spencer RR, Hurst PJ. A CMOS analog timing recovery circuit for PRML detectors. [Journal Paper] IEEE Journal of Solid-State Circuits, vol.35, no.1, Jan. 2000, pp.56-65. Publisher: IEEE, USA.
  23. Xiaodong Wang, Spencer RR. A CMOS two-path tree search detector. [Conference Paper] Proceedings of the IEEE 1999 Custom Integrated Circuits Conference (Cat. No.99CH36327). IEEE. 1999, pp.321-4. Piscataway, NJ, USA.
  24. Erdogan OE, Hurst PJ, Lewis SH. A 12-b digital-background-calibrated algorithmic ADC with -90-dB THD. [Conference Paper] IEEE. IEEE Journal of Solid-State Circuits, vol.34, no.12, Dec. 1999, pp.1812-20. USA.
  25. Wei-Shang Chu, Current KW. A CMOS voltage comparator with rail-to-rail input-range. [Conference Paper] Kluwer Academic Publishers. Analog Integrated Circuits & Signal Processing, vol.19, no.2, May 1999, pp.145-9. Netherlands.
  26. Xiaodong Wang, Spencer RR. A post-DFE path comparison detection algorithm. [Conference Paper] ICCT’98. 1998 International Conference on Communication Technology. Proceedings (IEEE Cat. No.98EX243). Publising House of Constr. Mater. Part vol.1, 1998, pp.159-63 vol.1. Beijing, China.
  27. Erdogan OE, Hurst PJ, Lewis SH. A 12 b digital-background-calibrated algorithmic ADC with -90 dB THD. [Conference Paper] 1999 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC. First Edition (Cat. No.99CH36278). IEEE. 1999, pp.316-17. Piscataway, NJ, USA.
  28. Le MQ, Hurst PJ, Dyer KC. An analog DFE for disk drives using a mixed-signal integrator. [Conference Paper] IEEE. IEEE Journal of Solid-State Circuits, vol.34, no.5, May 1999, pp.592-8. USA.
  29. Brown JEC, Hurst PJ, Rothenberg BC, Lewis SH. A CMOS adaptive continuous-time forward equalizer, LPF, and RAM-DFE for magnetic recording. [Journal Paper] IEEE Journal of Solid-State Circuits, vol.34, no.2, Feb. 1999, pp.162-9. Publisher: IEEE, USA.
  30. Dyer KC, Daihong Fu, Lewis SH, Hurst PJ. An analog background calibration technique for time-interleaved analog-to-digital converters. [Journal Paper] IEEE Journal of Solid-State Circuits, vol.33, no.12, Dec. 1998, pp.1912-19. Publisher: IEEE, USA.
  31. Daihong Fu, Dyer KC, Lewis SH, Hurst PJ. A digital background calibration technique for time-interleaved analog-to-digital converters. [Journal Paper] IEEE Journal of Solid-State Circuits, vol.33, no.12, Dec. 1998, pp.1904-11. Publisher: IEEE, USA.
  32. Le MQ, Hurst PJ, Dyer KC. An analog DFE for disk drives using a mixed-signal integrator. [Conference Paper] 1998 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.98CH36215). IEEE. 1998, pp.156-7. New York, NY, USA.
  33. Brown JEC, Hurst PJ. Continuous-time forward equalization for the decision-feedback-equalizer-based read channel. [Journal Paper] IEEE Transactions on Magnetics, vol.34, no.4, pt.2, July 1998, pp.2372-81. Publisher: IEEE, USA.
  34. Wei-Shang Chu, Current KW. A rail-to-rail input-range CMOS voltage comparator. [Conference Paper] Proceedings of Midwest Symposium on Circuits and Systems Dedicated to the Memory of Professor Mac Van Valkenburg (Cat. No.97CH36010). IEEE. Part vol.1, 1998, pp.160-3 vol.1. New York, NY, USA.
  35. Wei-Shang Chu, Current KW. Analog subcircuit maintenance in mixed-signal CMOS VLSI circuits. [Conference Paper] Proceedings of Midwest Symposium on Circuits and Systems Dedicated to the Memory of Professor Mac Van Valkenburg (Cat. No.97CH36010). IEEE. Part vol.1, 1998, pp.139-42 vol.1. New York, NY, USA.
  36. Xiaodong Wang, Spencer RR. A low-power 170-MHz discrete-time analog FIR filter. [Conference Paper] IEEE. IEEE Journal of Solid-State Circuits, vol.33, no.3, March 1998, pp.417-26. USA.
  37. Thanh CK, Lewis SH, Hurst PJ. A second-order double-sampled delta-sigma modulator using individual-level averaging. [Journal Paper] IEEE Journal of Solid-State Circuits, vol.32, no.8, Aug. 1997, pp.1269-73. Publisher: IEEE, USA.
  38. Current KW, McDonald CL. An adiabatic quaternary logic circuit. [Journal Paper] International Journal of Electronics, vol.83, no.1, July 1997, pp.55-9. Publisher: Taylor & Francis, UK.
  39. Rothenberg BC, Brown JEC, Hurst PJ, Lewis SH. A mixed-signal RAM decision-feedback equalizer for disk drives. [Journal Paper] IEEE Journal of Solid-State Circuits, vol.32, no.5, May 1997, pp.713-21. Publisher: IEEE, USA.
  40. Kajley RS, Hurst PJ, Brown JEC. A mixed-signal decision-feedback equalizer that uses a look-ahead architecture. [Conference Paper] IEEE. IEEE Journal of Solid-State Circuits, vol.32, no.3, March 1997, pp.450-9. USA.
  41. Shih T, Der L, Lewis SH, Hurst PJ. A fully differential comparator using a switched-capacitor differencing circuit with common-mode rejection. [Journal Paper] IEEE Journal of Solid-State Circuits, vol.32, no.2, Feb. 1997, pp.250-3. Publisher: IEEE, USA.
  42. Current KW, Hardaker WJ, Parker JF. A design tool for the fast prototyping of analog CMOS ICs. [Journal Paper] Journal of Microelectronic Systems Integration, vol.4, no.3, Sept. 1996, pp.137-47. Publisher: Plenum, USA.
  43. Brown JEC, Hurst PJ. Adaptive continuous-time forward equalization for DFE-based disk-drive read channels. [Conference Paper] Conference Record of The Twenty-Ninth Asilomar Conference on Signals, Systems and Computers. IEEE Comput. Soc. Press. Part vol.1, 1996, pp.668-72 vol.1. Los Alamitos, CA, USA.
  44. Rothenberg BC, Brown JEC, Hurst PJ, Lewis SH. A mixed-signal RAM decision-feedback equalizer for disk drives. [Conference Paper] 1996 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.96CH35943). Widerkehr & Associates. 1996, pp.180-1. Gaithersburg, MD, USA.
  45. Thanh C, Lewis SH, Hurst PJ. A 2/sup nd/-order double-sampled Delta Sigma modulator with individual-level averaging. [Conference Paper] 1996 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.96CH35943). Widerkehr & Associates. 1996, pp.100-1. Gaithersburg, MD, USA.
  46. Zeng RW, Hurst PJ. A comparison of noise-shaping clock generators for switched-capacitor filters. [Conference Paper] 1996 IEEE International Symposium on Circuits and Systems. Circuits and Systems Connecting the World, ISCAS 96 (Cat. No.96CH35876). IEEE. Part vol.1, 1996, pp.77-80 vol.1. New York, NY, USA.
  47. Kajley RS, Brown JEC, Hurst PJ. A mixed-signal decision-feedback equalizer that uses parallelism. [Conference Paper] Proceedings of the IEEE 1996 Custom Integrated Circuits Conference (Cat. No.96CH35886). IEEE. 1996, pp.17-20. New York, NY, USA.
  48. Brown JEC, Hurst PJ, Der L. A 35 Mb/s mixed-signal decision-feedback equalizer for disk drives in 2- mu m CMOS. [Journal Paper] IEEE Journal of Solid-State Circuits, vol.31, no.9, Sept. 1996, pp.1258-66. Publisher: IEEE, USA.
  49. Current KW, Hardaker WJ, Parker JE. A layout module generator for CMOS continuous-time filters. [Journal Paper] Journal of Microelectronic Systems Integration, vol.4, no.2, June 1996, pp.77-86. Publisher: Plenum, USA.
  50. Current KW, Oklobdzija VG, Maksimovic D. Low-energy logic circuit techniques for multiple valued logic. [Conference Paper] Proceedings. 1996 26th International Symposium on Multi-Valued Logic (Cat. No.96CB35950). IEEE Comput. Soc. Press. 1996, pp.86-90. Los Alamitos, CA, USA.
  51. Roo P, Spencer RR, Hurst PJ. Analog timing recovery architectures for PRML detectors. [Conference Paper] GLOBECOM ’95. Communications for Global Harmony. IEEE Global Telecommunications Conference. Technical Program Conference Record (Cat. No.95CH35756). IEEE. Part vol.1, 1995, pp.571-6 vol.1. New York, NY, USA.
  52. Parker JF, Current KW, Lewis SH. A CMOS continuous-time NTSC-to-color-difference decoder. [Journal Paper] IEEE Journal of Solid-State Circuits, vol.30, no.12, Dec. 1995, pp.1524-32. Publisher: IEEE, USA.
  53. Rothenberg BC, Lewis SH, Hurst PJ. A 20-Msample/s switched-capacitor finite-impulse-response filter using a transposed structure. [Journal Paper] IEEE Journal of Solid-State Circuits, vol.30, no.12, Dec. 1995, pp.1350-6. Publisher: IEEE, USA.
  54. Hurst PJ, Lewis SH. Determination of stability using return ratios in balanced fully differential feedback circuits. [Journal Paper] IEEE Transactions on Circuits & Systems II-Analog & Digital Signal Processing, vol.42, no.12, Dec. 1995, pp.805-17. Publisher: IEEE, USA.
  55. Brown JEC, Hurst PJ, Der L. A 35 Mb/s mixed-signal decision-feedback equalizer for disk-drive applications. [Conference Paper] Proceedings of the IEEE 1995 Custom Integrated Circuits Conference (Cat. No.95CH35775). IEEE. 1995, pp.563-6. New York, NY, USA.
  56. Burmas TV, Lewis SH, Hurst PJ, Dyer KC. A second-order double-sampled delta-sigma modulator. [Conference Paper] Proceedings of the IEEE 1995 Custom Integrated Circuits Conference (Cat. No.95CH35775). IEEE. 1995, pp.195-8. New York, NY, USA.
  57. Parker JF, Current KW, Lewis SH. A CMOS continuous-time NTSC-to-color-difference decoder. [Conference Paper] 1995 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC (Cat. No.95CH35753). IEEE. 1995, pp.294-5, 383. New York, NY, USA.
  58. Rothenberg BC, Lewis SH, Hurst PJ. A 20 Msample/s switched-capacitor finite impulse response filter in 2 mu m CMOS. [Conference Paper] 1995 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC (Cat. No.95CH35753). IEEE. 1995, pp.210-11, 369. New York, NY, USA.
  59. Berg SK, Hurst PJ, Lewis SH. An 80-Msample/s video switched-capacitor filter using a parallel biquadratic structure. [Journal Paper] IEEE Journal of Solid-State Circuits, vol.30, no.8, Aug. 1995, pp.898-905. USA.
  60. Lewis SH, Ramachandran R, Snelgrove WM. Indirect testing of digital-correction circuits in analog-to-digital converters with redundancy. [Journal Paper] IEEE Transactions on Circuits & Systems II-Analog & Digital Signal Processing, vol.42, no.7, July 1995, pp.437-45. USA.
  61. Current KW. Memory circuits for multiple valued logic voltage signals. [Conference Paper] Proceedings 1995 25th International Symposium on Multiple-Valued Logic (Cat. No.95CS35804). IEEE Comput. Soc. Press. 1995, pp.52-7. Los Alamitos, CA, USA.
  62. Current KW. Multiple-valued logic memory circuit. [Journal Paper] International Journal of Electronics, vol.78, no.3, March 1995, pp.547-55. UK.
  63. Hurst PJ, Rothenberg BC. A programmable clock generator that uses noise shaping and its application in switched-capacitor filters. [Journal Paper] IEEE Journal of Solid-State Circuits, vol.30, no.4, April 1995, pp.403-11. USA.
  64. Brown JEC, Hurst PJ, Agi I, Der L. Analog decision-feedback equalizer architectures. [Conference Paper] VLSI Signal Processing VII (Cat. No.94TH8008). IEEE. 1994, pp.266-75. New York, NY, USA.
  65. Kajley RS, Hurst PJ, Brown JEC. A mixed-signal decision-feedback equalizer using a look-ahead architecture. [Conference Paper] Conference Record of the Twenty-Eighth Asilomar Conference on Signals, Systems and Computers (Cat. No.94CH34546). IEEE Comput. Soc. Press. Part vol.2, 1994, pp.1413-17 vol.2. Los Alamitos, CA, USA.
  66. Current KW, Parker JF, Hardaker WJ. On behavioral modeling of analog and mixed-signal circuits. [Conference Paper] Conference Record of the Twenty-Eighth Asilomar Conference on Signals, Systems and Computers (Cat. No.94CH34546). IEEE Comput. Soc. Press. Part vol.1, 1994, pp.264-8 vol.1. Los Alamitos, CA, USA.
  67. Brown JEC, Hurst PJ, Der L, Agi I. A comparison of analog DFE architectures for disk-drive applications. [Conference Paper] 1994 IEEE International Symposium on Circuits and Systems (Cat. No.94CH3435-5). IEEE. Part vol.4, 1994, pp.99-102 vol.4. New York, NY, USA.
  68. Hurst PJ, Lewis SH. Simulation of return ratio in fully differential feedback circuits. [Conference Paper] Proceedings of the IEEE 1994 Custom Integrated Circuits Conference (Cat. No.94CH3427-2). IEEE. 1994, pp.29-32. New York, NY, USA.
  69. Current KW. Voltage-mode CMOS quaternary latch circuit. [Journal Paper] Electronics Letters, vol.30, no.23, 10 Nov. 1994, pp.1928-9. UK.
  70. Berg SK, Hurst PJ, Lewis SH, Wong PT. A switched-capacitor filter in 2 mu m CMOS using parallelism to sample at 80 MHz. [Conference Paper] 1994 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. First Edition (Cat. No.94CH3410-8). IEEE. 1994, pp.62-3. New York, NY, USA.
  71. Hurst PJ, Rothenberg BC. A programmable clock generator using noise shaping and its application in a switched-capacitor filter. [Conference Paper] 1994 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.94CH3434-8). IEEE. 1994, pp.105-6. New York, NY, USA.
  72. Current KW. Current-mode CMOS multiple-valued logic circuits. [Journal Paper] IEEE Journal of Solid-State Circuits, vol.29, no.2, Feb. 1994, pp.95-107. USA.
  73. Burmas TV, Dyer KC, Hurst PJ, Lewis SH. A second-order double-sampled delta-sigma modulator using additive-error switching. [Conference Paper] IEEE. IEEE Journal of Solid-State Circuits, vol.31, no.3, March 1996, pp.284-93. USA.
  74. Current KW, Parker J, Hardaker W. Block-diagram-level design capture, functional simulation, and layout assembly of analog CMOS ICs. [Conference Paper] (Proceedings) 1993 IEEE International Symposium on Circuits and Systems. IEEE. May 1993, pp.2090-3 vol.3. New York, NY, USA.
  75. Der L, Lewis SH, Hurst PJ. A switched-capacitor differencing circuit with common-mode rejection for fully differential comparators. [Conference Paper] Proceedings of the 36th Midwest Symposium on Circuits and Systems (Cat. No.93CH3381-1). IEEE. Part vol.2, 1993, pp.911-14 vol.2. New York, NY, USA.
  76. Current KW. Multiple valued logic: current-mode CMOS circuits. [Conference Paper] Proceedings of The Twenty-Third International Symposium on Multiple-Valued Logic (Cat. No.93CH3228-4). IEEE Comput. Soc. Press. 1993, pp.176-81. Los Alamitos, CA, USA.
  77. Matthews TW, Spencer RR. An integrated analog CMOS Viterbi detector for digital magnetic recording. [Journal Paper] IEEE Journal of Solid-State Circuits, vol.28, no.12, Dec. 1993, pp.1294-302. USA.
  78. Matthews TW, Spencer RR. An analog CMOS Viterbi detector for digital magnetic recording. [Conference Paper] 1993 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC. First Edition (Cat. No.93CH3272-2). IEEE. 1993, pp.214-15, 291. New York, NY, USA.
  79. Spencer RR, Worstell G. A spectrum analyzer laboratory project. [Journal Paper] IEEE Transactions on Education, vol.36, no.3, Aug. 1993, pp.301-6. USA.
  80. Hurst PJ, Levinson RA, Block DJ. A switched-capacitor delta-sigma modulator with reduced sensitivity to op-amp gain. [Journal Paper] IEEE Journal of Solid-State Circuits, vol.28, no.6, June 1993, pp.691-6. USA.
  81. Current KW. A CMOS latch circuit for multiple-valued bi-directional current signals. [Journal Paper] International Journal of Electronics, vol.74, no.5, May 1993, pp.717-25. UK.
  82. Current KW. Current-mode CMOS quaternary threshold logic full adder circuit. [Journal Paper] International Journal of Electronics, vol.74, no.4, April 1993, pp.587-91. UK.
  83. Agi I, Hurst PJ, Current KW. An image processing IC for backprojection and spatial histogramming in a pipelined array. [Journal Paper] IEEE Journal of Solid-State Circuits, vol.28, no.3, March 1993, pp.210-21. USA.
  84. Brown JEC, Hurst PJ, Der L. Design of an analog DFE for disk-drive applications. [Conference Paper] Conference Record of The Twenty-Sixth Asilomar Conference on Signals, Systems and Computers (Cat. No.92CH3245-8). IEEE Comput. Soc. Press. 1992, pp.965-9 vol.2. Los Alamitos, CA, USA.
  85. Agi I, Hurst PJ, Current KW. A 450 MOPS image backprojector and histogrammer. [Conference Paper] Proceedings of the IEEE 1992 Custom Integrated Circuits Conference (Cat. No.92CH3078-3). IEEE. 1992, pp.6.2/1-4. New York, NY, USA.
  86. Hurst PJ, Dyer KC. An improved double sampling scheme for switched-capacitor delta-sigma modulators. [Conference Paper] 1992 IEEE International Symposium on Circuits and Systems (Cat. No.92CH3139-3). IEEE. 1992, pp.1179-82 vol.3. New York, NY, USA.
  87. Agi I, Hurst PJ, Current KW. A pipelined VLSI chip architecture for real-time computed tomography of fan-beam data. [Conference Paper] 1992 IEEE International Symposium on Circuits and Systems (Cat. No.92CH3139-3). IEEE. 1992, pp.661-4 vol.2. New York, NY, USA.
  88. Lewis SH. Optimizing the stage resolution in pipelined, multistage, analog-to-digital converters for video-rate applications. [Journal Paper] IEEE Transactions on Circuits & Systems II-Analog & Digital Signal Processing, vol.39, no.8, Aug. 1992, pp.516-23. USA.
  89. Shieh E, Current KW, Hurst PJ, Agi I. High-speed computation of the Radon transform and backprojection using an expandable multiprocessor architecture. [Journal Paper] IEEE Transactions on Circuits & Systems for Video Technology, vol.2, no.4, Dec. 1992, pp.347-60. USA.
  90. Current KW. A current-mode CMOS algorithmic analog-to-quaternary converter circuit. [Conference Paper] Proceedings. The Twenty-Second International Symposium on Multiple-Valued Logic (Cat. No.92CH3113-8). IEEE Comput. Soc. Press. 1992, pp.229-34. Los Alamitos, CA, USA.
  91. Hurst PJ. A comparison of two approaches to feedback circuit analysis. [Journal Paper] IEEE Transactions on Education, vol.35, no.3, Aug. 1992, pp.253-61. USA.
  92. Worth AJ, Spencer RR. A neural network for tactile sensing: the Hertzian contact problem. [Journal Paper] IEEE Transactions on Systems, Man & Cybernetics, vol.22, no.1, Jan.-Feb. 1992, pp.177-82. USA.
  93. Haley SB, Hurst PJ. Authors’ reply to comments on ‘Pole and zero estimation in linear circuits’ by P. E. Gray and J. K. Matchett. [Journal Paper] IEEE Transactions on Circuits & Systems I-Fundamental Theory & Applications, vol.39, no.5, May 1992, pp.419. USA.
  94. Current KW. Current-mode CMOS latched quaternary threshold logic full adder. [Journal Paper] Electronics Letters, vol.28, no.13, 18 June 1992, pp.1273-5. UK.
  95. Current KW. Algorithmic analogue-to-quaternary convertor circuit using current-mode CMOS. [Journal Paper] Electronics Letters, vol.28, no.12, 4 June 1992, pp.1111-12. UK.
  96. Agi I, Hurst PJ, Jain AK. A VLSI processor for parallel contour tracing. [Journal Paper] IEEE Transactions on Signal Processing, vol.40, no.2, Feb. 1992, pp.429-38. USA.
  97. Spencer RR. Simulated performance of analog Viterbi detectors. [Journal Paper] IEEE Journal on Selected Areas in Communications, vol.10, no.1, Jan. 1992, pp.277-88. USA.
  98. Spencer RR. Analog implementations of artificial neural networks. [Conference Paper] 1991 IEEE International Symposium on Circuits and Systems (Cat. No.91CH3006-4). IEEE. 1991, pp.1271-4 vol.2. New York, NY, USA.
  99. Spencer RR. A parallel architecture for high-speed analog Viterbi detectors. [Conference Paper] Proceedings of the 33rd Midwest Symposium on Circuits and Systems (Cat. No.90CH2819-1). IEEE. 1991, pp.1030-3 vol.2. New York, NY, USA.
  100. Hsia TC, Current KW, Mao Z, Chu WS, Liu J, Lu GZ, Han WH. A proposed new VLSI architecture for real-time robot manipulator control. [Journal Paper] International Journal of Robotics & Automation, vol.6, no.4, 1991, pp.169-78. USA.
  101. Spencer RR, Hurst PJ. Analog implementations of sampling detectors. [Conference Paper] IEEE Transactions on Magnetics, vol.27, no.6, pt.1, Nov. 1991, pp.4516-21. USA.
  102. Hurst PJ, Brown JEC. Finite impulse response switched-capacitor filters for the delta-sigma modulator D/A interface. [Journal Paper] IEEE Transactions on Circuits & Systems, vol.38, no.11, Nov. 1991, pp.1391-7. USA.
  103. Hurst PJ. Exact simulation of feedback circuit parameters. [Journal Paper] IEEE Transactions on Circuits & Systems, vol.38, no.11, Nov. 1991, pp.1382-9. USA.
  104. Current KW, Hurlston ME. A bi-directional current-mode CMOS multiple valued logic memory circuit. [Conference Paper] Proceedings of the Twenty-First International Symposium on Multiple-Valued Logic (Cat. No.91CH3009-8). IEEE Comput. Soc. Press. 1991, pp.196-202. Los Alamitos, CA, USA.
  105. Hurst PJ. Shifting the frequency response of switched-capacitor filters by nonuniform sampling. [Journal Paper] IEEE Transactions on Circuits & Systems, vol.38, no.1, Jan. 1991, pp.12-19. USA.
  106. Spencer RR, Grishaw J. Simplified 1/f noise calculations. [Journal Paper] Electronics Letters, vol.27, no.4, 14 Feb. 1991, pp.312-14. UK.
  107. Current KW, Current JE. CMOS current-mode circuits for neural networks. [Conference Paper] 1990 IEEE International Symposium on Circuits and Systems (Cat. No.90CH2868-8). IEEE. 1990, pp.2971-4 vol.4. New York, NY, USA.
  108. Hurst P, Current KW, Agi I, Shieh E. A VLSI architecture for two-dimensional Radon transform computations. [Conference Paper] ICASSP 90. 1990 International Conference on Acoustics, Speech and Signal Processing (Cat. No.90CH2847-2). IEEE. 1990, pp.933-6 vol.2. New York, NY, USA.
  109. Hurst PJ, McIntyre WJ. Double sampling in switched-capacitor delta-sigma A/D converters. [Conference Paper] 1990 IEEE International Symposium on Circuits and Systems (Cat. No.90CH2868-8). IEEE. 1990, pp.902-5 vol.2. New York, NY, USA.
  110. Current KW. A CMOS quaternary threshold logic full adder circuit with transparent latch. [Conference Paper] Proceedings of the Twentieth International Symposium on Multiple-Valued Logic (Cat. No.90CH2886-0). IEEE Comput. Soc. Press. 1990, pp.168-73. Los Alamitos, CA, USA.
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