Stephen H. Lewis

Stephen H. Lewis

Professor

Phone:
(530) 752-0458
Email:
Website:
http://www.ece.ucdavis.edu/~lewis

Education

University of California, Berkeley, PhD, 1987
Stanford University, M.S., 1980
Rutgers University, B.S., 1979

Professional Experience

Professor, University of California, Davis, CA, 1999-Present
Associate Professor, University of California, Davis, CA, 1995-1999
Assistant Professor, University of California, Davis, CA, 1991-1995
Member of the Technical Staff, Bell Laboratories, Reading, PA, 1988-1991
Member of the Technical Staff, Bell Laboratories, Whippany, NJ, 1979-1982

Affiliation

Electrical and Computer Engineering Graduate Program

Research Interests

Analog integrated circuits, data conversion, filters, and signal processing.

Research Activities

Professor Lewis is interested in circuit design for data-conversion and signal-processing systems. The key objectives are to reduce system cost and increase portability, which will require both increased levels of integration and reduced power dissipations. Example projects include reference and buffer circuits, calibration of pipelined analog-to-digital converters and time-interleaved analog-to-digital-converter arrays.

Selected Publications

R. T. Perry, S. H. Lewis, A. Paul Brokaw, and T. R. Viswanathan, "A 1.4-V Supply CMOS Fractional Bandgap Reference," IEEE Journal of Solid-State Circuits, pp. 2180-2186, October 2007

N. J. Guilar, F. P.-K. Lau, P. J. Hurst, and S. H. Lewis, "A Passive Switched-Capacitor Finite-Impulse Response Equalizer," IEEE Journal of Solid-State Circuits, pp. 400-409, February 2007.

T.-H. Tsai, P. J. Hurst, and S. H. Lewis, "Bandwidth Mismatch and Its Correction in Time-Interleaved
Analog-to-Digital Converters," IEEE Transactions on Circuits and Systems II, pp. 1133-1137, October 2006.

G. Xing, S. H. Lewis, and T. R. Viswanathan, "A Unity-Gain Buffer with Reduced Offset and Gain Error," IEEE Custom Integrated Circuits Conference, pp. 825-828, September 2006.

J. P. Keane, P. J. Hurst, and S. H. Lewis, "Digital Background Calibration for Memory Effects in Pipelined Analog-to-Digital Converters," IEEE Transactions on Circuits and Systems I, pp. 511-525, March 2006.