Bevan M. Baas

Bevan M. Baas

Associate Professor

Phone:
(530) 746-8821
Email:
Website:
http://www.ece.ucdavis.edu/~bbaas

Education

Ph.D. in Electrical Engineering, Stanford University, Stanford, CA, 1999
M.S. in Electrical Engineering, Stanford University, Stanford, CA, 1990
B.S. in Electronic Engineering, California Polytechnic State University, San Luis Obispo, CA, 1987

Professional Experience

Associate Professor, University of California, Davis, Electrical & Computer Engineering, 2008-present
Assistant Professor, University of California, Davis, Electrical & Computer Engineering, 2002-2008
Visiting Professor, Circuit Research Lab, Intel Corporation, 2006
Digital Designer, Atheros Communications, Sunnyvale, CA, 1999-2001

Affiliation

Electrical and Computer Engineering Graduate Group
CITRIS

Research Interests

Algorithms, architectures, circuits, and VLSI design for high-performance, energy-efficient, and area-efficient computation with strong consideration of the challenges and opportunities of future fabrication technologies.

Research Activities

Dr. Baas' research activities involve the development and implementation of efficient and novel computational hardware with a focus on digital signal processing (DSP) workloads, which are becoming increasingly important in high-growth application areas from portable electronics to data-centers.

Active projects involve both programmable and dedicated-purpose processors. Recent projects include the AsAP (Asynchronous Array of simple Processors) programmable array processor chip, applications, compiler and mapping tools; Low Density Parity Check (LDPC) decoders; Fast Fourier Transform (FFT) processors; Viterbi decoders; and H.264 video encoders and decoders.

The 0.18 m CMOS AsAP chip contains 36 programmable processors, operates at over 610 MHz at 2.0 V, and is believed to be the highest clock rate processor designed in any university. The second generation AsAP2 processing platform contains 167 processors and has been implemented in 65 nm CMOS. It contains numerous architectural and circuit innovations and operates at over 1 GHz.

Distinctions

Bevan Baas was a National Science Foundation Fellow from 1990-93 and a NASA Graduate Student Researcher Fellow from 1993-96. He received the National Science Foundation CAREER award in 2006, and the Most Promising Engineer/Scientist Award by AISES in 2006.

Selected Publications

Dean Truong, Wayne Cheng, Tinoosh Mohsenin, Zhiyi Yu, Toney Jacobson, Gouri Landge, Michael Meeuwsen, Christine Watnik, Paul Mejia, Anh Tran, Jeremy Webb, Eric Work, Zhibin Xiao, Bevan Baas, "A 167-processor 65 nm Computational Platform with Per-Processor Dynamic Supply Voltage and Dynamic Clock Frequency Scaling," Symposium on VLSI Circuits, June 2008.

Zhiyi Yu and Bevan Baas, "High Performance, Energy Efficiency, and Scalability with GALS Chip Multiprocessors," IEEE Transactions of Very Large Scale Integration Systems (TVLSI), in press.

Zhiyi Yu, Michael Meeuwsen, Ryan Apperson, Omar Sattari, Michael Lai, Jeremy Webb, Eric Work, Dean Truong, Tinoosh Mohsenin, Bevan Baas, "AsAP: An Asynchronous Array of Simple Processors," IEEE Journal of Solid-State Circuits (JSSC), vol. 43, no. 3, pp. 695-705, March 2008.

Ryan Apperson, Zhiyi Yu, Michael Meeuwsen, Tinoosh Mohsenin, Bevan Baas, "A Scalable Dual-Clock FIFO for Data Transfers between Arbitrary and Haltable Clock Domains," IEEE Transactions of Very Large Scale Integration Systems (TVLSI), vol. 15, no. 10, pp. 1125-1134, October 2007.

Tinoosh Mohsenin, Bevan M. Baas, "High-Throughput LDPC Decoders Using A Multiple Split-Row Method," In Proceedings of the IEEE International Conference on Acoustics, Speech, and Signal Processing (ICASSP '07), April 2007.