- (530) 752-5545
Ph.D. in Computer Science and Engineering, University of Michigan, Ann Arbor, 1998.
M.S. in Computer Engineering, Northeastern University, Boston, 1993.
B.E. (with distinction) in Computer and Communications Engineering, American University of Beirut, Lebanon, 1991.
Associate Professor, University of California, Davis, 2008 - Present.
Assistant Professor, University of California, Davis, 1998 - 2008.
Research Assistant, University of Michigan, Ann Arbor, 1994 - 1998.
Teaching Assistant, Northeastern University, Boston, 1992 - 1993.
Electrical and Computer Engineering Graduate Group
Computer-aided design, verification, and testing for digital systems; Fault-tolerant computing; and VLSI architectures.
Professor Al-Asaad's research focuses on the comprehensive lifetime validation of digital systems that uses fabrication fault testing and simulation techniques and accounts for design errors, fabrication faults, and operational faults. The specific contributions of his research activities include: (1) efficient techniques for gate-level and high-level simulation-based design verification, (2) new post silicon verification methods that improve the observability of internal signals within complex digital systems, (3) several on-line testing techniques for the detection of operational faults during normal operation, (4) various approximate and exact global fault collapsing techniques that drastically reduce the number of modeled faults, and (5) new implementation-independent functional test generation techniques that extract good sets of functional vectors.
In addition to the above, Professor Al-Asaad conducts research in Fault-Tolerant Computing where he has made significant contributions especially in the fields of time redundant task-scheduling and reconfigurable fault-tolerant processor arrays.
Hussain Al-Asaad received the highly-competitive and prestigious NSF Career Award in 2001. He also received the Professor of the Year Award (given by the IEEE chapter at UC-Davis) in 2001. He was elected to IEEE Senior member in 2005.
J. Campos and H. Al-Asaad, "A novel mutation-based validation paradigm for high-level hardware descriptions", to appear in IEEE Transactions on VLSI, 2008.
H. Al-Asaad, "Efficient global fault collapsing for combinational library modules", Proc. International Conference on Computer Design (CDES), 2007, pp. 37-43.
J. Campos and H. Al-Asaad, "Concurrent design error simulation for high-level microprocessor implementations", Proc. Autotestcon, 2004, pp. 382-388.
H. Al-Asaad and J. P. Hayes, "Logic design verification via simulation and automatic test pattern generation", Journal of Electronic Testing: Theory and Applications, Vol. 16, No. 6, pp. 575-589, December 2000.
H. Al-Asaad and J. P. Hayes, "ESIM: A multimodel design error and fault simulator for logic circuits", Proc. VLSI Test Symposium, 2000, pp. 221-228.