Venkatesh Akella

Venkatesh Akella

Professor

Phone:
(415) 347-5764
Email:
Website:
http://www.ece.ucdavis.edu/~akella/

Education

Ph. D. in Computer Science, Univeristy of Utah, Salt Lake City, Utah, 1992
M.S. in Electrical & Communication Engineering, Indian Institute of Science, Bangalore, 1988

Professional Experience

Professor, University of California, Davis, Electrical & Computer Engineering, 2006-Present
Associate Professor, University of California, Davis, Electrical & Computer Engineering, 1998-2006
Visiting Professor, Indian Institute of Management(IIM), Bangalore, India, 1999
Visiting Professor, Hewlett-Packard Company, Roseville, California, Summer 1996
Assistant Professor, University of California, Davis, Electrical & Computer Engineering, 1992-1998

Affiliation

Electrical and Computer Engineering Graduate Group

Research Interests

Computer Architecture and Parallel Computing, Embedded Systems, Hardware/Software Codesign, Reconfigurable Computing, FPGA, Functional Programming and Asynchronous Circuits, Software Engineering, Electronic Commerce, Location-Aware Computing, Computational Biology and Optical Interconnects.

Research Activities

The goal of Prof. Akella's research is to create models, platforms (architectures) and design methodologies to support high performance and low power computing requirements applications such as networking, location aware services, multimedia, compression, error correction, scientific computation and computational biology. The central premise of the research is that reducing cost and maximizing flexibility are absolutely critical for making computing systems accessible to a broader audience and in turn to have the maximum impact on our society. Hardware/software codesign and exploiting the tradeoffs between resource utilization and quality of results have emerged as common themes to develop programmable architectures and design methodologies to address the requirements of many probolems.

Prof. Akella's current research involves exploring the use of optical interconnects to overcome the processor memory latency and bandwidth bottlenecks in multicore processors, developing systematic design methodologies to accelerate error-floor simulation for error correcting codes and techniques for developing and deploying embedded software to facilitate location aware computing.

Selected Publications

John Oliver, Rajeevan Amirtharajah, Venkatesh Akella, Frederic T. Chong" Credit-Based Dynamic Reliability Management using Online Wearout Detection", ACM International Conference on Computing Frontiers, 2008.

John Oliver, Rajeevan Amirtharajah, Venkatesh Akella, Fred Chong and Roland Geyer, Life Cycle Aware Computing: Reusing Silicon Technology?, IEEE Computer, December 2007.

Ravishankar Rao, Justin Wenck, Diana Franklin, Raj Amirtharajah and Venkatesh Akella, Segmented Bitline Cache, High Performance Computing - HiPC 2006, 13th International Conference, Bangalore, India, December 18-21, 2006, Proceedings. Lecture Notes in Computer Science 4297 Springer 2006.

Ravishankar Rao, Justin Wenck, Diana Franklin, Raj Amirtharajah and Venkatesh Akella, Exploiting Non-Uniform Memory Access Patterns through Bit-line Segmentation, ACM SIGMICRO Letters Volume 24, Number 1, 2006. (Selected top papers from 4th Workshop on Memory Performance Improvement, WMPI 2006)

John Oliver, Ravishankar Rao, Paul Sultana, Jedidiah Crandall, Erik Czernikowski, Leslie W. Jones IV, Diana Keen, Venkatesh Akella, and Frederic T. Chong, Synchroscalar: A Multiple Clock Domain Power Aware Tile-Based Embedded Processor, International Symposium on Computer Architecture, ISCA, June 2004