Cellphone Re-use to reduce E-Waste

Three million tons of household electronics were thrown out in the United State in 2006. Many of items were cell phones that were discarded despite being functional and useful. These problem leads to the exposure toxic materials (e.g. batteries) to the environment and an increased carbon footprint. The goal of this research is to make reusing electronics as simple as reusing a glass jar. The repurposing of cell phone poses several engineering research challenges:

  • Harvesting environmental energy to power the phone to eliminate servicing.
  • Software which adapts to unreliable hardware and variable power.
  • Hardware design which supports reusability after the phone is re-purposed.
  1. Tang Lung Cheung, Kari Okamoto, Frank Maker III, Xin Liu and Venkatesh Akella,"Markov Decision Process (MDP) Framework for Optimizing Software on Mobile Phones", International Conference on Embedded Software, CS & ECE Dept, UC Davis, 2009.
Researchers: Frank Maker, Ashkan Eghttesadi

Circuit Design for Energy Harvesting Power Supplies

Current work focuses on developing flexible digital and analog circuits to operate on the AC power supplies provided dircectly from vibration-based energy scavengers. Uing AC power directly eliminates the energy waste associated with AC/DC conversion. Taking advantage of this energy savings requires ciruits and architectures that can operate and adapt to a varying supply voltage and varying available power. Self-timed circuits, energy aware algorithms, and robust memories are some of the techniques currently being researched and tested:

  • Self-timed circuits are used to ensure that clocking for digital circuits tracks changes in process, temperature, and voltage (PVT).
  • Energy aware or energy adaptable algorithms, such as distributed arithmatic (DA), allow numerical precision to scale with available power. This allows low precision results to computed when traditional algorithms could not produce any result with the available power.
  • Robust memories are being developed that allow data to be retained without refresh or adequate supply voltage for extend periods of time. Current research has developed a DRAM array that can retain data for 1.2 ms without refreshing.
Researchers: Justin Wenck

Energy Scalable Computational Array for Energy Harvesting Sensors

Harvesting energy from environmental sources can extend wireless sensor network node lifetime beyond the limits of battery technology. However, the output power from an energy harvester is highly variable. Our research is to design and implement an energy efficient and energy scalable computational array which maximizes sensor performance by matching system power consumption to the available scavenged energy through power scalable approximate signal processing. The array consists of distributed arithmetic (DA) based functional units coupled with a reconfigurable interconnect structure. Each functional unit can be configured to perform a set of linear and nonlinear signal processing functions in an area efficient manner which also minimizes leakage power. The sensor DSP flowgraphs are realized on the array by assigning an appropriate function to each computational unit and configuring the interconnect structure. Currently, we are at the second iteration of the micro-architecture design of the functional unit and our circuit work is focused on evaluating several low-swing driver and receiver circuit combinations and coding techniques to address interconnect power. We are also exploring using energy recovery circuits to further reduce the array's power consumption. A custom integrated circuit will ultimately be implemented to validate our architecture, communication, and circuit concepts.

  1. R. Amirtharajah,"An Energy Scalable Computational Array for Sensor Signal Processing" (invited), 2006 ISSCC Special Topic Session on Power-Aware Signal Processing, 5 February 2006.
  2. J. Collier,"Memory and Low-Swing Interconnect for Energy Harvesting Circuit Applications", M.S. Thesis, ECE Dept. UC Davis, 2005.
  3. B. Zhou,"Memory Design for Energy Scalable Reconfigurable Logic", M.S. Thesis, ECE Dept. UC Davis, 2004.
Researchers: Liping Guo, Mackenzie Scott

Energy Scalable DC/DC Conversion

We are developing a novel approach to implement very low power DC/DC conversion for battery-operated and energy harvesting systems with applications in biomedical devices, portable electronics, and wireless sensor networking. The system consists of a buck converter with a mixed-signal sliding-mode controller. This approach shows promise in terms of decreasing power consumption and providing energy scalability: the ability to trade off power for output voltage quality. In this case, figures of merit for the output include voltage ripple, conversion efficiency, and settling time.

Researcher: Nate Guilar

Integrated Solar Energy Harvesting and Storage

To explore integrated solar energy harvesting as a power source for low power systems, an array of energy scavenging photodiodes based on a passive-pixel architecture for CMOS imagers has been fabricated together with storage capacitors implemented using on-chip interconnect in a 0.35 micron CMOS logic process. Integrated vertical plate capacitors enable dense energy storage without limiting optical efficiency. Measurements show 225 microW/mm2 output power generated by a light intensity of 20k LUX.

  1. N. Guilar, A. Chen, T. Kleeburg, and R. Amirtharajah, "Integrated Solar Energy Harvesting and Storage", 2006 International Symposium on Low Power Electronics and Design, October 2006, to appear.
Researchers: Nate Guilar, Travis Kleeburg, Albert Chen

Mechanical Vibration Energy Harvesters: Models, Circuit Interfaces, and Control

Energy harvesting and recovery schemes exploiting piezoelectric materials such as PZT can help address the growing gap between silicon performance and battery energy density by providing a complementary source of energy for system operation. The primary challenge is that the voltage and power output of a PZT scavenging device is variable, both in magnitude and frequency. To improve energy scavenging system design, we are developing equivalent circuit models for piezoelectric vibration-based energy harvesters and incorporating them into standard circuit simulators. We plan to extend this work by exploring low-power mixed-signal circuits which can monitor the energy harvester output and provide feedback to scale system power consumption with the available energy

Researchers: Andrew Chang, Nate Guilar

Energy Scalable Distributed Arithmetic on FPGAs

Energy scalability is a system feature which allows the user to trade off energy consumption for some metric of performance, such as clock frequency or output signal-to-noise ratio. Previous work has focused on custom hardware for energy scalability. However, increasing design complexity and time-to-market pressures drive more and more digital designs to Field-Programmable Gate Array (FPGA) implementation. This research develops software and architectures for implementing energy scalable DSP on commercial FPGAs.

Researcher: Zulfi Ansari

Nanoscale Sensor Circuit Interfaces and Architectures

Novel nanoscale materials such as carbon nanotubes and silicon nanowires are promising candidates for low power and highly sensitive gas sensors. Applications include environmental monitoring, industrial process control, and homeland security. Current projects underway with this focus include:

  • Investigating the feasibility of sigma-delta ADCs as a lower power interface between nano-scale sensors and their digital interconnects. Initially this will involve developing models that will characterize ADC performance vs. power consumption requirements. Using these models, we hope to design a sigma-delta ADC that will minimize power consumption by taking advantage of the low speed nature of the sensor application. In addition, we will also be investigating techniques to suppress sensor noise by processing the signal before the ADC, or, if possible, taking advantage of the noise shaping capabilities of the signal-delta ADC itself.
  1. Darshan D. Thaker, Albert Chen, Rajeevan Amirtharajah and Frederic T. Chong,"On Designing Self-Calibrating Nanoscale Sensors that Adaptively Invest Power for Accuracy", IEEE International Workshop on Design and Test of Defect-Tolerant Nanoscale Architectures, (NanoArch 05) 2005
  2. R. Amirtharajah, A. Chen, D. Thaker, and F. T. Chong, "Circuit Interfaces and Optimization for Resistive Nanosensors," (invited) Proc. of SPIE, Vol. 6008: Nanosensing: Materials and Devices II, 23-26 October 2005, pp. 60080J1-15.
Researchers: Albert Chen, Jeffrey Loo

Computer Architecture Projects

Past and current projects and collaborations in computer architecture.

  1. R. Rao, J. Wenck, D. Franklin, R. Amirtharajah, and V. Akella, "Exploiting Non-Uniform Memory Access Patterns Through Bitline Segmentation," 4th Workshop on Memory Performance Issues (WMPI-2006), 11 February, 2006.
  2. D. D. Thaker, R. Amirtharajah, F. Impens, I. L. Chuang and, F. T. Chong, "Recursive TMR: Scaling Fault Tolerance in the Nanoscale Era," IEEE Design & Test of Computers, Vol. 22, Issue 4, July-Aug. 2005, pp. 298-305.
  3. D. D. Thaker, F. Impens, I. L. Chuang, R. Amirtharajah, and F. T. Chong, "On Using Recursive TMR as a Soft Error Mitigation Technique," 2005 Workshop on the System Effects of Logic Soft Errors (SELSE-1), 5-6 April 2005.