Microprocessor Design in the Nanoscale Era

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Friday, November 16, Giedt Hall 1003, 12:00pm-1:00pm

Speaker: Stefan Rusu
Intel

Host: Professor Bevan Baas

Abstract:

Moore's Law has fueled the worldwide technology revolution for over 40 years and will continue to drive higher feature integration in leading-edge microprocessors with multiple cores and larger on-die caches. CMOS process technology will continue its historical scaling trend, while research activities are focusing on novel devices and manufacturing techniques. Process, voltage and temperature variations are driving a paradigm shift from a deterministic to a probabilistic design methodology. Active and leakage power will remain the main limiters for both server and client processors. This presentation will review several techniques to control switching power and leakage with practical examples from Intel designs. Continued improvements in packaging technology enhance the cooling capabilities, while providing better power delivery and higher pin counts.

Biography:

Stefan Rusu received the MSEE degree from the Polytechnic University in Bucharest, Romania. His industry experience includes 21 years with Intel Corp. and 6 years at Sun Microsystems. He is presently a Senior Principal Engineer in the Intel Architecture Development Group leading the technology and special circuits design for the Xeon(r) Processors. Stefan has authored over 90 papers on VLSI circuit technology and holds 35 U.S. patents. He is an IEEE Fellow and a member of the Technical Program Committee for ISSCC, ESSCIRC and A-SSCC conferences. Stefan is an Associate Editor of the IEEE Journal of Solid-State Circuits and an elected member of the SSCS AdCom.


Speaker contact information

* Please contact Bevan Baas , if you would like to meet the speaker.

Stefan Rusu
Senior Principal Engineer
Intel

About the seminar:
This seminar is part of the Fall EEC 290 seminar series and is open to all.