A Case for Many-Core Processor Arrays

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Friday, February 24, Giedt Hall 1003, 12:10pm-1:00pm

Speaker: Bevan Baas
Associate Professor
University of California, Davis

Host: Professor Anh-Vu Pham


Future fabrication technologies are expected to provide ever-increasing numbers of available devices but both system-level and chip-level power constraints will limit achievable throughputs--thus highlighting the criticalness of energy-efficient design. Die device counts in the 100s of millions and billions virtually guarantee designs will have many processors and the most interesting research questions deal with how the available devices and wires are organized into 100s and 1000s of processing elements per die.

The most high performance, energy efficient, and smallest area designs will have processing units matched to their computational kernels in terms of datapath complexity, data memory requirements, and instruction stream requirements. Further optimized designs will match their supply voltage and clock frequency to the processor's instantaneous workload demands.

The Asynchronous Array of Simple Processors (AsAP) is a programmable and reconfigurable processing system that: enables high throughput and high energy-efficiency, is well matched to many DSP, multimedia, and embedded workloads. It is also well-suited for deep submicron VLSI fabrication technologies. AsAP is composed of a large number of programmable reduced-complexity processing elements with individual digitally-tunable clock oscillators operating completely independently with respect to each other (GALS).

A 65 nm CMOS design contains 167 processors and has many new architectural features including dedicated FFT, Viterbi, and video motion estimation processors. The programmable processors are able to individually and dynamically change their clock frequency and supply voltage (choosing among VddHi, VddLo, or disconnected). The chip is fully-functional with measurements showing the programmable processors operating up to 1.2 GHz which is believed to be the highest clock rate fabricated processor designed in any university.

Several dozen DSP and general tasks have been coded plus more complex applications including: AES encryption engines, a full-rate 1080p 30fps HDTV residual encoder, a fully-compliant IEEE 802.11a/11g Wi-Fi wireless LAN baseband transmitter and receiver, and a large portion of the mid- and back-end processing for a medical ultrasound unit. Power, throughput, and area results compare very well with solutions on existing programmable DSP processors.

On-going research projects here at UC Davis in applications, architectures, circuits, and VLSI will be highlighted.


Bevan Baas received M.S. and Ph.D. degrees in electrical engineering from Stanford University in 1990 and 1999 respectively. After graduation, he joined Atheros Communications as the second full-time employee after the founders and served as a core member of the team which developed the first IEEE 802.11a (54 Mbps, 5 GHz) Wi-Fi solution. In 2003, he joined the Department of Electrical and Computer Engineering at the University of California, Davis where he is now an Associate Professor.

Dr. Baas was an NSF Fellow from 1990-93 and a NASA GSR Fellow from 1993-96. He received the National Science Foundation CAREER award in 2006, the Most Promising Engineer/Scientist Award by AISES in 2006, and the Best Paper Award at the IEEE Intl Conf on Computer Design in 2011. Since 2007 has has been an Associate Editor for the IEEE Journal of Solid-State Circuits. He has served and is serving as: Program Committee Co-Chair of the IEEE HotChips Symposium on High-Performance Chips in 2011 and Program Committee member 2009-10; Co-Chair of the 2011 Design Automation Conference (DAC) Workshop on Parallel Algorithms, Programming, and Architectures; Technical Program Committee member of the International Conference on Computer Design (ICCD) 2004-05, 2007-09; Technical Program Committee member of the IEEE International Symposium on Asynchronous Circuits and Systems in 2010; International Solid-State Circuits Conference (ISSCC) Student Research Preview Committee member in 2012; IEEE Micro Guest Editor, and Design & Test Guest Editor in 2012; and a member of the Technical Advisory Board of an early stage technology company.