SRAM Variability in Space and Time

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Friday, October 28, Storer Hall 1322, 12:10pm-1:00pm

Speaker: Borivoje Nikolic
University of California, Berkeley

Host: Professor Anh-Vu Pham


Increased process and device variability presents a major challenge for future SRAM scaling. Fast and accurate validation of SRAM read stability and writeability margins is crucial for estimating yield in large SRAM arrays. Conventional static SRAM read/write metrics are characterized through test structures that are able to provide limited hardware measurement data and cannot be used to investigate cell bit fails in functional SRAM arrays. As an alternative, distributions of minimum operating voltage (Vmin) are often used to characterize SRAM robustness. This talk reviews our recent work on large-scale characterization of read stability and writeability in functional SRAM arrays using direct bit-line measurements in 45nm CMOS. It also establishes a relationship between the static noise margin distributions and Vmin. The static noise measurement structures are augmented to characterize variability of SRAM robustness in time due to the effects of random telegraph noise (RTS) and bias temperature instability.


Borivoje Nikolic received the Dipl.Ing. and M.Sc. degrees in electrical engineering from the University of Belgrade, Serbia, in 1992 and 1994, respectively, and the Ph.D. degree from the University of California at Davis in 1999.

His research activities include digital and analog integrated circuit design and VLSI implementation of communications and signal processing algorithms. He is a scientific co-director of the Berkeley Wireless Research Center. For work with his students and colleagues he received the best paper awards at the ISSCC, Symposium on VLSI Circuits, ISLPED, International SOI Conference and ESSDERC.