Sustainable Silicon: Energy-Efficient VLSI Interconnects

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Friday, March 4, Giedt Hall 1002, 12:00pm-1:00pm

Patrick Chiang
Assistant Professor, Oregon State University

Host: Professor Anna Scaglione


For more than 40 years, Moore's law has accurately predicted the doubling of transistor density approximately every two years. This continued technology scaling will enable massive integration of parallelism on a single die, such as thousands of computational cores on a many-core processor.Unfortunately, the energy required to communicate between these units at every level (on-chip, off-chip, wireless) will be the critical consumer of the system power.As Professor Dally (Stanford) quoted in 1998, "Computation is free; communication is expensive."

The goal of the OSU-VLSI research group is to develop energy-efficient, VLSI interconnect circuits and systems that will facilitate future power-constrained computing.In this talk, I will describe current research in improving upon the state-of-the-art in energy efficiency (pJ/b) of both wireline and wireless VLSI signaling for two end applications.

  1. Megawatt, Exascale Datacenters -- Working in collaboration with Intel and the Department of Energy, we are exploring the design of a next-generation supercomputer by 2018, delivering a 100x improvement in performance [10 petaflops/sec in 2011: 1 exaflops/sec in 2018) within the same power budget (20MW).In 2008, the DARPA exascale study concluded that the main roadblock is the interconnect: "it may be easier to solve the power problem associated with base computation than it will be to reduce the problem of transporting data from one site to another - on the same chip, between closely coupled chips in a common package, or between different racks on opposite sides of a large machine room". Hence, we are investigating:

    1. Energy-Efficient On-Chip Wires: Because both V_DD and wire capacitance have essentially stopped scaling with CMOS technology, the energy (CV^2 ) consumed by an on-chip inverter has also been pegged (~150fJ/b/mm).In this talk, I will describe two measured testchips that improve on-chip interconnect energy by approximately 4x (40fJ/b/mm) and 40x (4fJ/b/mm).The first is a network-on-a-chip prototype that combines both architectural and circuit techniques to reduce on-chip interconnect power.The second chip approaches the fundamental limits to low-voltage swing on-chip signaling.

    2. Sub-1mW/Gbps Off-Chip Links: The power consumption of off-chip links (i.e. CPU->Memory; CPU->CPU) is critical for future many-core systems, as increased data bandwidth is required to keep functional units busy.We will present two 8Gbps serial link receivers that achieve measured energy-efficiencies of 0.6mW/Gbps and 0.16mW/Gbps, approximately 5x better than current state-of-the-art.Injection-locking and near-threshold operation are utilized to improve the energy consumed by both clock generation and phase interpolation.

  2. Batteryless, 'Wireless Bandaids' -- Working with gerontology clinicians at the Linus Pauling Institute and the Oregon Center for Aging and Technology at OHSU medical school, we are developing a wearable wireless sensor that continuously monitors the effects of vitamins on aging and cognitive decline.While our 1^st generation design using off-the-shelf components is currently undergoing clinical trials, our vision is a low-cost, disposable 'wireless bandaid' system-on-chip.This microchip will non-invasively collect vital-sign signals (heart-ECG or brain-EEG), process the information, and wirelessly transmit this information to a local basestation without requiring a battery (SoC power < 100uW).Because the design of the wireless transceiver dominates the system power budget, I will describe recent progress towards achieving short-range, micropowered wireless communications, utilizing both self-healing process adaptation and injection-locked ultrawideband receiver synchronization.


Patrick Chiang received the B.S. degree in electrical engineering and computer sciences from the University of California, Berkeley, in 1998, and the M.S. and Ph.D. degrees in electrical engineering from Stanford University in 2001 and 2007. He is currently an assistant professor of electrical and computer engineering at Oregon State University.

In 1998, he was with Datapath Systems (now LSI Logic), working on analog front-ends for DSL chipsets. In 2002 he was a research intern at Velio Communications (now Rambus) working on 10GHz clock synthesis architectures. In 2004 he was a consultant at startup Telegent Systems, evaluating low phase noise VCOs for CMOS mobile TV tuners. In 2006 he was a visiting NSF postdoctoral researcher at Tsinghua University, China, investigating low power, low voltage RF transceivers. In Summer 2007, he was a visiting professor at the Institute of Computing Technology, Chinese Academy of Sciences. He is currently a visiting professor at Fudan University, Shanghai, China, working on short-range UWB transceivers.

He is the recipient of the 2010 Department of Energy Early CAREER Award titled "Sustainable Silicon -- Energy-Efficient VLSI Interconnect for Extreme-Scaling Computing". He is an associate editor of the IEEE Transactions on Biomedical Circuits and Systems.