Making Sense Out of Variability in Scaled CMOS

November 9, 2007
Borivoje (Bora) Nikolic, Electrical Engineering Division Operations, University of California, Berkeley


Abstract:
This talk describes sources of variability in sub-100nm CMOS and methods for its characterization. Test chip measurements show that systematic, process-induced variations dominate in 90nm CMOS. Methods for modeling and mitigating the variations in the design will be presented as well, focusing on compensating for systematic variations and exploiting spatial correlations.


Bio:
Borivoje Nikolic received the Dipl.Ing. and M.Sc. degrees in electrical engineering from the University of Belgrade, Yugoslavia, in 1992 and 1994, respectively, and the Ph.D. degree from the University of California at Davis in 1999. He is an Associate Professor of Electrical Engineering and Computer Sciences, at the University of California at Berkeley. His research activities include digital and analog integrated circuits and VLSI implementation of communications and signal processing algorithms.