Nanoscale Transistors: Speed or Talent?Professor Savas Kaya, School of EE & CS, Ohio University
The minimum feature size in today's CMOS-based integrated circuits has already reached to sub-100nm scale. These systems are also the most complicated, nano-scale 'functional' products ever fabricated. The experience gained and problems encountered in such large-scale systems are invaluable in guiding the evolution of nanosystems. An important class of problems in this regard is associated with the fluctuation phenomena, which deal with the stochastic variation of device performance due to microscopic mismatches among the fabricated devices. It is well understood now that random distribution of dopants causes intrinsic fluctuations in device characteristics and can impede the traditional scaling approach in sub-100 nm MOSFETs. However, other stochastic effects that do not scale with geometry, such as oxide thickness variations (OTV) or line edge roughness (LER) can also contribute to intrinsic fluctuations. In fact the granularity of matter is a fundamental limit that will persist even in well-scaled undoped devices immune to fluctuations due to discrete electrical charges. An efficient way to combat fluctuations in nanotransistors is to either include redundancy in the system design or allow corrective actions for system performance. In this talk, I will give examples of tunable analog and reconfigurable digital circuits built using DG-MOSFETs, a new class of devices that allow dynamic control of threshold voltage. I will emphasize that, in light of parameter fluctuations, power limits and area concerns, the future nano-systems must have reconfigurable architectures, which can already be addressed using DG-MOSFETs, without having to wait for fundamental material breakthroughs.
Savas Kaya (M01) graduated from Istanbul Technical University in 1992 with a BSc in Electronics and Communication Engineering, received M.Phil. degree in 1994 from the University of Cambridge, U.K., and Ph.D. degree in 1998 from Imperial College of Science, Technology & Medicine, London, U.K., for his work on strained Si quantum wells on vicinal substrates. From 1998 to 2001, he was a Postdoctoral Researcher at the University of Glasgow, Scotland, U.K., carrying out research in transport and scaling in Si/SiGe MOSFETs, and fluctuation phenomena in decanano MOSFETs. He is currently with the Russ College of Engineering, Ohio University, Athens, OH. He has served as Air Force Office of Scientific Research Summer Faculty Fellow in . He has over 30 journal papers and 45 conference proceedings. His other interests include nanocircuits, TCAD, transport theory, nanostructures, process integration, ionic transport and biomolecular modelling in trans-membrane proteins. Dr. Kaya was a member of the organizing committee for IWCE7, 2000, and IEEE Nanotech6, .