EEC180B - Digital Systems II

5 units - Fall and Spring Quarters

Lecture: 3 hours

Laboratory: 6 hours

Prerequisite: Courses 110A, 180A.

Grading: Letter

Catalog Description: Computer-aided design of digital systems with emphasis on hardware description languages (VHDL), logic synthesis, and field-programmable gate arrays (FPGA). May cover advanced topics in digital system design such as static timing analysis, pipelining, memory system design, testing digital circuits.

Relationship to Outcomes:
 Students who have successfully completed this course should have achieved:

Course Outcomes ABET Outcomes
An ability to apply knowledge of mathematics, science, and engineering A
An ability to design and conduct experiments, as well as to analyze and interpret data B
An ability to design a system, component, or process to meet desired needs within realistic constraints such as economic, environmental, social, political, ethical, health and safety, manufacturability, and sustainability C
An ability to identify, formulate, and solve engineering problems E
An ability to use the techniques, skills, and modern engineering tools necessary for engineering practice. K

Expanded Course Description

  1. Review of basic topics in logic design
    • Boolean Algebra
    • Combinational Logic Design and Optimization
    • Flip-flops and Latches
    • Sequential Logic Design and optimization
  2. VHDL
    • Structural modeling
    • Dataflow modeling
    • Simulation Cycle
    • Modeling data in VHDL
    • Modeling Combinational Logic and State Machines
    • Advanced topics in VHDL libraries, packages, attributes
  3. Computer-aided design of digital circuits
    • Design Flow
    • Functional Simulation
    • Overview of logic synthesis and technology mapping
    • Timing Simulation
  4. Field Programmable Gate Arrays
    • Architecture of FPGA
    • Programmable logic blocks and Programmable interconnect schemes
    • Detailed Study of Xilinx, Altera, and Actel FPGA architectures
    • FPGA-based design flow
  5. Timing Analysis and Clocking Schemes
    • Static timing analysis concepts
    • Edge-triggered flip-flops
    • Level-sensitive latches
  6. Design Implementation and Optimization
    • Control/Data Separation
    • Pipelining
    • Retiming
  7. Memory System Design
    • SRAM
    • DRAM
    • Interfacing Memory to a Microprocessor Bus
  8. Advanced Topics (Optional)
    • Processor Design
    • Arithmetic Circuit Design
    • Hardware Testing and Design for Testability

Textbook: Digital Systems Design Using VHDL, Charles H. Roth Jr., PWS Publishing Company, 1998. The Designer's Guide to VHDL by Peter J. Ashenden, Morgan-Kauffman Publisher, 1995 Contemporary Logic Design by Randy Katz, Benjamin Cummings, 1993

Computer Use: The class will require extensive use of workstations and PCs.

Laboratory Projects:

  1. Powerview Tutorial
  2. Xilinx Tutorial
  3. ALU and Register File Design
  4. Memory Interface Design
  5. Using a Logic Analyzer
  6. Controller for the Pipelined Microprocessor
  7. Download to Xilinx FPGA and Testing

Engineering Design Statement:
 The course involves the design, implementation, and verification of a simple pipelined RISC microprocessor. In the first two weeks the students will learn the CAD tools by way of tutorials. In the following laboratory periods the students will design the various components of a microprocessor. In the last two weeks of class the students will implement the design in a Xilinx FPGA and verify its operation. The students will use tools for schematic capture, logic simulation, combinational logic optimization, timing analysis, and FPGA-based design. The course mimics modern design methodologies for FPGA-based design and has a significant design content.

Professional Component: Engineering Depth, Laboratory
Engineering Science: 3 units
Engineering Design: 2 units

Updated: 7/09