EEC118 - Digital Integrated Circuits

4 units - Spring Quarter

Lecture: 3 hours

Laboratory: 3 hours

Prerequisites: Courses 110A, 180A

Grading: Letter

Catalog Description: Analysis and design of digital integrated circuits. The emphasis is on MOS logic circuit families. Logic gate construction, voltage transfer characteristics, and propagation delay. Regenerative circuits, RAM's, ROM's, and PLA's.

Relationship to Outcomes:
Students who have successfully completed this course should have achieved:

Course Outcomes ABET Outcomes
An ability to apply knowledge of mathematics, science, and engineering A
An ability to design and conduct experiments, as well as to analyze and interpret data B
An ability to identify, formulate, and solve engineering problems E
An ability to use the techniques, skills, and modern engineering tools necessary for engineering practice. K

Expanded Course Description:

  1. The Ideal Logic Gate, Definitions
    1. Logic levels, noise margins
    2. Switching speed
    3. Review of basic logic functions and symbols
  2. The MOS Transistor
    1. Large signal equations and models, regions of operation
    2. Static I-V characteristics
    3. Device capacitances
    4. CMOS processes, parasitics
  3. Interconnect
    1. Wire parasitics
    2. Wire models
  4. MOS Logic Gates
    1. Resistively loaded inverter, load line analysis, voltage transfer characteristic
    2. NMOS and pseudo-NMOS inverter
    3. The CMOS inverter
    4. Static CMOS logic
    5. Dynamic CMOS logic 
    6. Pass transistor logic
    7. Low power design
    8. Arithmetic structures
  5. Switching Time Analysis of CMOS Logic
    1. Definition of propagation delay times
    2. Piecewise linear analysis for estimating switching times
    3. Calculation of the equivalent load capacitance
    4. Logical effort
    5. Driving long interconnects
  6. Regenerative Logic Circuits, Sequential Elements, and Clocking
    1. A simple bistable circuit
    2. SR latch, D flip-flop
    3. Static and dynamic flip-flops
    4. Estimating switching speed of regenerative circuits
    5. One-, Two-, and Four-Phase clocking
  7. Semiconductor Arrays and Memories
    1. The PLA
    2. ROM
    3. EPROM and nonvolatile memory
    4. RAM - Static and dynamic storage cells
    5. Address decoders and sense amplifiers
  8. Physical Design
    1. Gate arrays
    2. Standard cells
    3. VLSI layout
  9. Advanced and Alternative Topics
    1. Bipolar and BiCMOS logic gates
    2. The Schmitt trigger
    3. Multivibrators
    4. Self-timed and asynchronous techniques
    5. Differential logic styles 

Textbook: J. Rabaey, A. Chandrakasan, and B. Nikoli, Digital Integrated Circuits: A Design Perspecitve, Prentice Hall. 

Illustrative Reading: 

  1. S-M. Kang and Y. Leblebici, CMOS Digital Integrated Circuits: Analysis and Design, Mcgraw-Hill.
  2. N. Weste and D. Harris, CMOS VLSI Design: A Circuits and Systems Perspective, Addison-Wesley.

Computer Use:
Students will use SPICE and/or Cadence tools to complere several laboratory exercises. These include the transistor-level design and simulation of combinational and sequencial logic elements, arithmetic structures, and memory cells. 

Laboratory Projects:
Labs consist of three-hour experiments that reinforce the lecture material, provide hands-on experience with test equipment, CAD tools, and simulators, and require some design calculations. 

  1. MOS transistor characteristics, measurement of large signal parameters
  2. Characteristics of CMOS inverters, CMOS NOR gate, ring oscillators, propagation delay
  3. Logic gate design and simulation using computer-aided design tools
  4. Design, simulation, and measurement of D flip-flops
  5. Design and simulation of arithmetic circuits
  6. Design and simulation of memory circuits

Engineering Design Statement
Digital integrated circuit design will be covered with an emphasis on MOS. Topics will include: the MOS transistor operation, large signal models, MOS gates, propagation delay calculation, regenerative circuits and sequential elements, ROM, PLA, RAM. There will be three-hour laboratories approximately each week. Some laboratories. involve physical experiments and others rely on circuit simulation. The course teaches digital transistor-level circuit design, discussing trade-offs in speed, area, robustness, and power that can be realized by transistor sizing, choice of circuit topology, clocking methodology, etc.

Professional Component: Engineering Breadth
Engineering Science: 2 units
Engineering Design: 2 units