The design of an asynchronously shared memory module for the AsAP platform is presented. AsAP consists of a 2-dimensional array of processing elements with limited memory resources. The memory module expands the storage capacity available to AsAP processors, enabling the mapping of applications with large working sets. The memory module described shares an 8 K-word SRAM among four processors, but can support a 64 K-word SRAM with no additional changes. The memory module is independently clocked, supports hardware address generation, mutual exclusion, and multiple addressing modes. Simultaneous access by different processors is arbitrated using a least-recently-serviced priority scheme. A standard cell implementation of the memory module cycles at 555 MHz and occupies 1.2 mm2 in 0.18 μm CMOS.
Michael J. Meeuwsen, "A Shared Memory Module for an Asynchronous Array of Simple Processors," Technical Report ECE-CE-2005-2, Computer Engineering Research Laboratory, ECE Department, University of California, Davis, 2005.
@mastersthesis{meeuwsen:msthesis,
author = {Michael J. Meeuwsen},
title = {A Shared Memory Module for an Asynchronous Array of Simple
Processors},
school = {University of California},
year = 2005,
address = {Davis, CA, USA},
month = apr,
note = {\url{http://www.ece.ucdavis.edu/cerl/techreports/2005-2/}}
}