Fast Fourier Transforms on a Distributed Digital Signal Processor

Omar Sattari
Masters Thesis
Computer Engineering Research Laboratory
Department of Electrical and Computer Engineering
University of California, Davis
Technical Report ECE-CE-2004-7, Computer Engineering Research Laboratory, University of California, Davis, 2004.

Abstract:

Fast Fourier Transforms are used in a variety of Digital Signal Processing applications. As semiconductor process technology becomes more refined, the ability to implement faster and more efficient FFTs increases. However, due to the high costs and design time of custom FFT processors, implementation of the FFT on programmable or reconfigurable platforms is practical. In this work, we present mappings of FFTs of various lengths to a programmable, reconfigurable array of processors. The design of hardware address generators is also presented, as it is tightly coupled with implementation of the Fast Fourier Transform. The reconfigurable array of processors is named Asynchronous Array of Simple Processors (AsAP). A Register Transfer Level (RTL) model of the AsAP architecture is used to simulate Fast Fourier Transforms. Coding for the FFTs is done primarily with assembly-level code. Three FFTs of length 32, 64, and 1024 points were mapped and simulated onto AsAP. The accuracy of each FFT was verified by comparing simulation results to an independent model.

Paper

Reference

Omar Sattari, "Fast Fourier Transforms on a Distributed Digital Signal Processor," Technical Report ECE-CE-2004-7, Computer Engineering Research Laboratory, ECE Department, University of California, Davis, 2004.

BibTeX entry

@mastersthesis{sattari:msthesis,
   author      = {Omar Sattari},
   title       = {Fast Fourier Transforms on a Distributed Digital 
                  Signal Processor},
   school      = {University of California},
   year        = 2004,
   address     = {Davis, CA, USA},
   month       = sep,
   note        = {\url{http://www.ece.ucdavis.edu/cerl/techreports/2004-7/}}
   }

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