Arithmetic Units for a High Performance Digital Signal Processor

Michael A. Lai
Masters Thesis
Computer Engineering Research Laboratory
Department of Electrical and Computer Engineering
University of California, Davis
Technical Report ECE-CE-2004-6, Computer Engineering Research Laboratory, University of California, Davis, 2004.

Abstract:

An Arithmetic Logic Unit (ALU) and a Multiply-Accumulate (MAC) unit designed for a high performance digital signal processor are presented. The 16-bit ALU performs all the logic instructions and includes a saturating adder and subtractor. It also performs shift instructions and a bit reverse instruction. The MAC unit is pipelined into three stages and includes a 40-bit accumulator. It utilizes Modified Booth's algorithm, reduces the partial product tree with rows of 4:2 compressors and half adders, and produces the final result with a 40-bit carry select adder. The MAC unit also contains a 40-bit right shifter for the accumulator. Both units are laid out and tested in the TSMC 0.18 um process. The ALU can be clocked at 398 MHz and the MAC unit can be clocked at 611 MHz at a supply voltage of 1.8 V and a temperature of 40 C.

Paper

Reference

Michael A. Lai, "Arithmetic Units for a High Performance Digital Signal Processor," Technical Report ECE-CE-2004-6, Computer Engineering Research Laboratory, ECE Department, University of California, Davis, 2004.

BibTeX entry

@mastersthesis{lai:msthesis,
   author      = {Michael A. Lai},
   title       = {Arithmetic Units for a High Performance Digital Signal 
                 Processor},
   school      = {University of California},
   year        = 2004,
   address     = {Davis, CA, USA},
   month       = sep,
   note        = {\url{http://www.ece.ucdavis.edu/cerl/techreports/2004-6/}}
   }

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