First-In First-Out (FIFO) memory structures are widely used to buffer the transfer of data between processing blocks. High performance and high complexity digital systems increasingly are required to transfer data between modules of differing and even unrelated clock frequencies. This thesis presents an encompassing description of the motivation and design decisions for a robust and scalable dual-clock FIFO architecture. It also investigates the hardware design issues involved in this architecture through the custom CMOS circuit design of the dual-clock FIFO architecture. The proposed design utilizes an efficient and low-latency memory array structure and can operate in applications where multiple clock cycles of latency exist between the data producer, FIFO, and the data consumer. This feature is increasingly relevant in high-speed designs where multiple clock cycles are not uncommonly needed to transmit data between major processing blocks. It also includes a configurable synchronization circuit that robustly synchronizes asynchronous signals within the FIFO.
Ryan W. Apperson, "A Dual-Clock FIFO for the Reliable Transfer of High-Throughput Data Between Unrelated Clock Domains," Technical Report ECE-CE-2004-5, Computer Engineering Research Laboratory, ECE Department, University of California, Davis, 2004.
@mastersthesis{apperson:msthesis,
author = {Ryan W. Apperson},
title = {A Dual-Clock {FIFO} for the Reliable Transfer of
High-Throughput Data Between Unrelated Clock Domains},
school = {University of California},
year = 2004,
address = {Davis, CA, USA},
month = sep,
note = {\url{http://www.ece.ucdavis.edu/cerl/techreports/2004-5/}}
}