Mapping an FIR Filter to a 2-Dimensional Mesh of Processors

Abstract:

This report presents and analyzes results of mapping an FIR filter algorithm onto a 2-Dimensional (2-D) Digital Signal Processing (DSP) processor array. The variation in throughput and hardware requirements over changing topologies is examined over a total of seven major topologies and eighty-five specific mappings. Performance results and mapping suggestions are also given.

Paper

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Reference

Howard CheHao Chang and Bevan M. Baas, "Mapping an FIR Filter to a 2-Dimensional Mesh of Processors," Technical Report ECE-CE-2003-1, Computer Engineering Research Laboratory, ECE Department, University of California, Davis, 2003.

BibTeX entry

@TechReport{Chang:2003:MFF,
   author =      {Howard CheHao Chang and Bevan M. Baas},
   title =       {Mapping an {FIR} Filter to a 2-Dimensional Mesh of 
                  Processors},
   institution = {Computer Engineering Research Laboratory, ECE Department,
                  University of California, Davis},
   year =         2003,
   number =      {ECE-CE-2003-1},
   note =        {\url{http://www.ece.ucdavis.edu/cerl/techreports/2003-1/}}
   }