IMPLEMENTING SELF-TIMED CIRCUITS IN FIELD PROGRAMMABLE GATE
ARRAYS
Field Programmable Gate Arrays (FPGAs) offer fast prototyping of
digital circuits, and could be valuable for testing a new
methodology like self-timed design. However, FPGAs that are
currently in the market do not implement asynchronous circuits
effectively. This is shown by implementing asynchronous logic in a
Xilinx 4000 series FPGA. A list of line delay constraints for a
hazard-free implementation of the self-timed modules in a LUT-based
FPGA is formulated and the conditions under which the cell set is
hazard-free is explained. An FPGA architecture (PGA-STC) and the
relevant technology mapping tool for implementing two-phase
transition based signaling with bundled-data self-timed circuits are
proposed. PGA-STC is unique in being able to implement both data
and control sections of asynchronous systems efficiently and without
hazards, using a programmable delay element.
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