Asynchronous Systems Research Group

ASRG

Introduction
Research Group Memebers
Technical Papers
Asynchronous Links

Introduction

At ASRG, students and professors conduct research in the emerging field of asynchronous VLSI system design. Here we attempt to address both the theoretical aspects of asynchronous system design, as well as applying that theory to design high-performance and low-power VLSI ASICs.

This work is currently proceeding in ...

• An Asynchronous Discrete Cosine Transform Processor : The DCT plays a central role in many of today's popular image compression algorithms. This investigation presents a highly pipelined architecture with asynchronous control circuitry.

• A Field Programmable Gate Array for implementing self-timed circuits : PGA-STC will implement asynchronous circuits optimally and has the capability to handle the various hazards that asynchronous design introduces.

• Fast Radix-4 Floating Point Divider using self-timed techniques.

• Asynchronous Dispatch Stack (ADS): Counterflow pipeline based dynamic insruction scheduling techniques for asynchronous superscalar processors.

• Dynamic Clock Gating methodologies.

Research Group Members

Venkatesh Akella

Jonathan B. Lipsher

Kapilan Maheswaran

David Johnson

Tony Werner

Robert Gluss

Navjyot Birak

Brett Stott

Nithya Raghavan

Technical Papers

• J.B. Lipsher, The Asynchronous Discrete Cosine Transform Processor Core, MS Thesis.[129 pages]
  With increased interest in low power consumption and design modularity, asynchronous digital systems present us with an attractive alternative design paradigm. This thesis investigates the conceptual advantages and practical realities of a synchronous system design through its application to a Discrete Cosine Transform (DCT) processor. The DCT plays a central role in many of today's popular image compression algorithms...

  K. Maheswaran, Implementing Self-Timed Circuits in Field Programmable Gate Arrays, MS Thesis.

  K. Maheswaran & V. Akella, PGA-STC: Programmable Gate Array for Implementing Self-Timed Circuits. [18 pages - under construction]

  FPGAs offer fast prototyping of digital circuits, and could be valuable for testing a new methodology like self-timed design. However, FPGAs that are currently in the market do not implement asynchronous circuits effectively. This paper describes an FPGA architecture called PGA-STC and the tools associated with it as a solution. An appendix of related schematics and simulations is available.

  K. Maheswaran & V. Akella, Hazard-free implementation of the self-timed cell set for the Xilinx 4000 Series FPGA.[15 pages]

  This paper deals with the hazard-free implementation of asynchronous logic in a Xilinx 4000 series FPGA. More specifically, a list of line delay constraints for a hazard-free implementation of the self-timed modules is presented and the conditions under which the cell is hazard-free is explained. An appendix of related schematics, the hazard-free self-timed cell set and example circuits are also available.

  K. Maheswaran & J.B. Lipsher, A Cell Set for Self-Timed Design Using Xilinx XC4000 Series FPGA. [6 pages]

  Basic event-logic modules were designed for building self-timed circuits and systems using Xilinx 4000 Series FPGAs. This cell set is designed to be used with the VIEWlogic Workview and the Xilinx XACT tools.

  J.B. Lipsher & K. Maheswaran, A 4-Bit Asynchronous Pipelined Multiplier in the Xilinx 4000 Series FPGA.[13 pages]

  This report serves to both verify the correctness of our self-timed cell set for the Xilinx FPGA architecture, and to demonstrate a fully-functional asynchronous system which has been realized in hardware.

  Venkatesh Akella, An Integrated Framework for High-level Synthesis of Self-timed Circuits. PhD Thesis [152 pages].

  Venkatesh Akella & Ganesh Gopalakrishnan, SHILPA: A High Level Synthesis System for Self-timed Circuits.[42 pages]

  Detailed version of ICCAD-92 paper.

  Venkatesh Akella & Ganesh Gopalakrishnan, Flow Analysis Techniques in High Level Asynchronous Circuit Synthesis.[23 pages]

  Expanded version of TAU-92 paper.

Asynchronous Links

Eindhoven University of Technology, Netherlands

Parallelism & Algorithms

University of Edinburgh

Asynchronous/Self-timed FPGA systems

University of Manchester, England

AMULET: First asynchronous implementation of a commercial microprocessor (ARM)

University of Manitoba, Canada

Another Asynchronous Multiplier on the Xilinx FPGA

University of Utah

VLSI Architectures & CAD for VLSI Architechtures

University of Washington

MONTAGE: First FPGA for asynchronous circuits

University of Waterloo, Canada

Models & Algorithms for Synthesis, Verification, and Testing of Integrated Circuits

Other Asynchronous Logic Groups